DMCA
An Efficient Deterministic Test Pattern Compaction Scheme Using Modified IC Scan Chain
BibTeX
@MISC{Novák_anefficient,
author = {Ondřej Novák and Jan Hlavička},
title = {An Efficient Deterministic Test Pattern Compaction Scheme Using Modified IC Scan Chain},
year = {}
}
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Abstract
In this paper, we propose a new scheme for Built-In Self-Test (BIST) that uses an LFSR obtained by adding feedback loops to the IC boundary scan chain. This LFSR first generates random patterns to cover easy-to-test faults and after the random testing phase it is partially loaded with seeds to generate deterministic vectors for hard-to-test faults. The seeds are obtained by solving systems of linear equations for seed variables, respecting the positions where the test patterns have specified values. The scan chain based LFSR due to its length produces sequences with very low probability of linear dependence of generated patterns. This would hardly be achievable using an added external LFSR, whose length has to be minimized due to the cost limitations. The probability of encoding a test pattern into a seed is the same as in the case of using multiple polynomial LFSR, but the hardware overhead is lower. Fault coverage for the ISCAS benchmark circuits was simulated and an optimized testing strategy for fully scanned ICs was proposed on the basis of the obtained results. The test patterns in mixed-mode testing are obtained partially from a hardware TPG and partially from a software ATPG tool, where the hardware TPG tests the Test/Shift
Keyphrases
test pattern hardware tpg test shift hard-to-test fault lfsr first generates linear equation obtained result built-in self-test new scheme scan chain added external lfsr seed variable software atpg tool low probability hardware overhead easy-to-test fault ic boundary scan chain fault coverage linear dependence multiple polynomial lfsr cost limitation optimized testing strategy feedback loop deterministic vector iscas benchmark circuit mixed-mode testing
