BibTeX
@MISC{Dai_acceleratingnetwork-on-chip,
author = {Wenbo Dai and Natalie Enright Jerger},
title = {Accelerating Network-on-Chip Simulation via Sampling},
year = {}
}
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Abstract
Abstract—Architectural complexity continues to grow as we consider the large design space of multiple cores, cache architectures, networks-on-chip and memory controllers for emerging architectures. Simulators are growing in complexity to reflect each of these system components. However, many full-system simulators fail to take advantage of the underlying hardware resources such as multiple cores; as a result, simulation times have grown significantly in recent years. Long turnaround times limit the range and depth of design space exploration that is tractable. Communication has emerged as a first class design consideration and has led to significant research into networks-on-chip (NoC). The NoC is yet another component of the architecture that must be faithfully modeled in simulation. Given its importance, we focus on accelerating NoC simulation through the use of sampling techniques; sampling can provide both accurate results and fast evaluation. We propose NoCLabs and NoCPoint, two sampling methodologies utilizing statistical sampling theory and traffic phase behavior, respectively. Experimental results show that our proposed NoCLabs and NoCPoint estimate NoC performance with an average error of 5 % while achieving one order of magnitude speedup on average. I.
Keyphrases
network-on-chip simulation multiple core turnaround time magnitude speedup simulation time significant research noc simulation cache architecture average error system component abstract architectural complexity hardware resource noc performance design space exploration accurate result memory controller many full-system simulator fast evaluation traffic phase behavior recent year large design space first class design consideration experimental result
