Memory bandwidth limitations of future microprocessors

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Memory bandwidth limitations of future microprocessors (1996)

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by Doug Burger , James R. Goodman , Alain Kägi

Venue:	IN PROCEEDINGS OF THE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
Citations:	226 - 12 self

BibTeX

@INPROCEEDINGS{Burger96memorybandwidth,
    author = {Doug Burger and James R. Goodman and Alain Kägi},
    title = {Memory bandwidth limitations of future microprocessors},
    booktitle = {IN PROCEEDINGS OF THE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE},
    year = {1996},
    pages = {78--89},
    publisher = {}
}

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Abstract

This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory latencies do so at the expense of increased bandwidth requirements. Using a decomposition of execution time, we show that for modern processors that employ aggressive memory latency tolerance techniques, wasted cycles due to insufficient bandwidth generally exceed those due to raw memory latencies. Given the importance of maximizing memory bandwidth, we calculate effective pin bandwidth, then estimate optimal effective pin bandwidth. We measure these quantities by determining the amount by which both caches and minimal-traffic caches filter accesses to the lower levels of the memory hierarchy. We see that there is a gap that can exceed two orders of magnitude between the total memory traffic generated by caches and the minimal-traffic caches—implying that the potential exists to increase effective pin bandwidth substantially. We decompose this traffic gap into four factors, and show they contribute quite differently to traffic reduction for different benchmarks. We conclude that, in the short term, pin bandwidth limitations will make more complex on-chip caches cost-effective. For example, flexible caches may allow individual applications to choose from a range of caching policies. In the long term, we predict that off-chip accesses will be so expensive that all system memory will reside on one or more processor chips.

Keyphrases

future microprocessor memory bandwidth limitation effective pin bandwidth minimal-traffic cache memory latency system memory traffic reduction bandwidth requirement pin bandwidth potential exists insufficient bandwidth long term aggressive memory latency tolerance technique total memory traffic modern processor processor chip short term pin bandwidth limitation memory hierarchy execution time optimal effective pin bandwidth traffic gap different benchmark critical consideration off-chip access complex on-chip cache memory bandwidth individual application flexible cache

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