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High-performance asynchronous pipeline circuits (1996)
| Venue: | In Proc. Int. Symp. on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer |
| Citations: | 29 - 2 self |
BibTeX
@INPROCEEDINGS{Yun96high-performanceasynchronous,
author = {Kenneth Y. Yun and Peter A. Beerel Y and Julio Arceo},
title = {High-performance asynchronous pipeline circuits},
booktitle = {In Proc. Int. Symp. on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer},
year = {1996},
publisher = {Society Press}
}
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Abstract
This paper presents design and simulation results of two high-performance asynchronous pipeline circuits. The rst circuit is a two-phase micropipeline but uses pseudo-static Svensson-style double edge-triggered D-ip- ops (DETDFF) for data storage in place of traditional transmission gate latches or Sutherland's capture-pass latches. The second circuit is a fourphase micropipeline with burst-mode control circuits. We compare our DETDFF and four-phase implementations of a FIFO bu er with the current stateof-the-art micropipeline implementation using fourphase controllers designed by Dayand Woods for the AMULET-2 processor. We implemented Day and Woods's design and both of our designs in the MO-SIS 1:2 m CMOS process and simulated them with a 4.6V power supply and at 100 C. Our SPICE simulations show that our DETDFF and four-phase designs have 70 % and 30 % higher throughput respectively than Day and Woods's design. This higher throughput for the DETDFF design is due to latching the data on both edges of the latch control, removing the need of a reset phase and simplifying the control structures. Our four-phase design, on the other hand, has higher throughput because of the simpli ed control structures and the removal of the latch enable bu ers from the critical path. The four-phase design, though not quite as fast as the DETDFF design, requires much smaller area for data storage. 1
Keyphrases
high-performance asynchronous pipeline circuit four-phase design data storage detdff design critical path current stateof-the-art micropipeline implementation power supply burst-mode control circuit rst circuit fourphase micropipeline second circuit latch control two-phase micropipeline cmos process traditional transmission gate latch spice simulation dayand wood fifo bu er four-phase implementation reset phase latch enable bu er amulet-2 processor fourphase controller simulation result simpli ed control structure capture-pass latch
