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Selective Eager Execution on the PolyPath Architecture (1998)
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| Venue: | In Proceedings of the 25th Annual International Symposium on Computer Architecture |
| Citations: | 72 - 3 self |
BibTeX
@INPROCEEDINGS{Klauser98selectiveeager,
author = {Artur Klauser and Abhijit Paithankar and Dirk Grunwald},
title = {Selective Eager Execution on the PolyPath Architecture},
booktitle = {In Proceedings of the 25th Annual International Symposium on Computer Architecture},
year = {1998},
pages = {250--259}
}
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Abstract
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an execution model to overcome mis-speculation penalties by executing both paths after diffident branches. We present the micro-architecture of the PolyPath processor, which is an extension of an aggressive superscalar, out-of-order architecture. The PolyPath architecture uses a novel instruction tagging and register renaming mechanism to execute instructions from multiple paths simultaneously in the same processor pipeline, while retaining maximum resource availability for single-path code sequences. Results of our execution-driven, pipeline-level simulations show that SEE can improve performance by as much as 36% for the go benchmark, and an average of 14% on SPECint95, when compared to a normal superscalar, out-of-order, speculative execution, monopath processor. Moreover, our architectural model is both eleg...
Keyphrases
polypath architecture selective eager execution control-flow misprediction penalty speculative execution novel instruction tagging diffident branch architectural model pipeline-level simulation processor pipeline high performance go benchmark present selective eager execution mis-speculation penalty multiple path monopath processor execution model aggressive superscalar major impediment maximum resource availability wide-issue superscalar processor single-path code sequence polypath processor out-of-order architecture
