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A Design Space Evaluation of Grid Processor Architectures (2001)
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BibTeX
@MISC{Nagarajan01adesign,
author = {Ramadass Nagarajan and Karthikeyan Sankaralingam and Doug Burger and Stephen W. Keckler},
title = { A Design Space Evaluation of Grid Processor Architectures},
year = {2001}
}
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Abstract
In this paper, we survey the design space of a new class of architec-tures called Grid Processor Architectures (GPAs). These architectures are designed to scale with technology, allowing faster clock rates than conventional architectures while providing superior instruction-level parallelism on traditional workloads and high performance across a range of application classes. A GPA consists of an array of ALUs, each with limited control, connected by a thin operand network. Pro-grams are executed by mapping blocks of statically scheduled instruc-tions to the ALU array and executing them dynamically in dataflow or-der This organization enables the critical paths of instruction blocks to be executed on chains of ALUs without transmitting temporary val-ues back to the register file, avoiding most of the large, unscalable structures that limit the scalability of conventional architectures. Fi-nally, we present simulation results of a preliminary design, the GPA-1. With a half-cycle routing delay, we obtain performance roughly equal to an ideal 8-way, 512-entry window superscalar core. With no inter-ALU delay, perfect memory, and perfect branch prediction, the 1PC of the GPA-1 is more than twice that of the ideal superscalar core, achieving an average of 11 IPC across nine SPEC CPU2000 and Mediabench benchmarks.
Keyphrases
grid processor architecture design space evaluation conventional architecture superior instruction-level parallelism critical path ideal superscalar core new class clock rate inter-alu delay spec cpu2000 mediabench benchmark half-cycle routing delay perfect memory design space application class 512-entry window superscalar core high performance perfect branch prediction register file alu array limited control present simulation result thin operand network temporary val-ues instruction block unscalable structure preliminary design traditional workload dataflow or-der
