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P.: Combining analytical and empirical approaches in tuning matrix transposition (2006)
| Venue: | In: Proc. Parallel Architectures and Compilation Techniques (PACT |
| Citations: | 6 - 1 self |
BibTeX
@INPROCEEDINGS{Lu06p.:combining,
author = {Qingda Lu and Sriram Krishnamoorthy},
title = {P.: Combining analytical and empirical approaches in tuning matrix transposition},
booktitle = {In: Proc. Parallel Architectures and Compilation Techniques (PACT},
year = {2006},
pages = {233--242}
}
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Abstract
Matrix transposition is an important kernel used in many applications. Even though its optimization has been the subject of many studies, an optimization procedure that targets the characteristics of current processor architectures has not been developed. In this paper, we develop an integrated optimization framework that addresses a number of issues, including tiling for the memory hierarchy, effective handling of memory misalignment, utilizing memory subsystem characteristics, and the exploitation of the parallelism provided by the vector instruction sets in current processors. A judicious combination of analytical and empirical approaches is used to determine the most appropriate optimizations. The absence of problem information until execution time is handled by generating multiple versions of the code- the best version is chosen at runtime, with assistance from minimal-overhead inspectors. The approach highlights aspects of empirical optimization that are important for similar computations with little temporal reuse. Experimental results on PowerPC G5 and Intel Pentium 4 demonstrate the effectiveness of the developed framework. Categories and Subject Descriptors D.3.4 [Programming Languages]: Processors—code generation; compilers; optimization
Keyphrases
matrix transposition empirical approach integrated optimization framework approach highlight aspect many application memory misalignment important kernel optimization procedure intel pentium minimal-overhead inspector many study vector instruction set similar computation judicious combination problem information little temporal reuse empirical optimization current processor architecture programming language memory subsystem characteristic memory hierarchy execution time powerpc g5 current processor multiple version subject descriptor appropriate optimization developed framework experimental result effective handling
