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A Memory Efficient, Programmable Multi-Processor Architecture For Real-Time Motion Estimation Type Algorithms (1995)
BibTeX
@MISC{Greef95amemory,
author = {E. De Greef and F. CATTHOOR and H. DE MAN},
title = {A Memory Efficient, Programmable Multi-Processor Architecture For Real-Time Motion Estimation Type Algorithms},
year = {1995}
}
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Abstract
. In this paper, an architectural template is presented, which is able to execute the full search motion estimation algorithm or other similar video or image processing algorithms in real time. The architecture is based on a set of programmable video signal processors (VSP's). It is also possible to integrate everything on a chip set using VSP cores. Due to the programmability, the system is very flexible and can be used for emulation of other similar block-oriented local-neighborhood algorithms. The architecture can be easily divided into several partitions, without data-exchange between partitions. Special attention is paid to memory size and transfer optimization, which are dominant factors for both area and power cost. KEYWORDS. Architectural template, block-oriented video algorithms, programmable VSP's, interconnection network, memory size and transfer optimization. 1 INTRODUCTION In video applications, several block-oriented local-neighborhood-dependent algorithms with simple co...
Keyphrases
programmable multi-processor architecture memory efficient real-time motion estimation type algorithm memory size architectural template special attention several partition programmable vsp block-oriented video algorithm similar block-oriented local-neighborhood algorithm video application image processing algorithm transfer optimization real time programmable video signal processor simple co full search motion estimation algorithm similar video interconnection network power cost several block-oriented local-neighborhood-dependent algorithm dominant factor vsp core
