DMCA
Reduced-bandwidth multithreaded algorithms for sparse matrix-vector multiplication (2011)
| Venue: | In Proc. IPDPS |
| Citations: | 22 - 0 self |
BibTeX
@INPROCEEDINGS{Buluç11reduced-bandwidthmultithreaded,
author = {Aydın Buluç and Samuel Williams and Leonid Oliker and James Demmel},
title = {Reduced-bandwidth multithreaded algorithms for sparse matrix-vector multiplication},
booktitle = {In Proc. IPDPS},
year = {2011}
}
Share
 |
 |
 |
 |
||
OpenURL
Abstract
Abstract—On multicore architectures, the ratio of peak memory bandwidth to peak floating-point performance (byte:flop ratio) is decreasing as core counts increase, further limiting the performance of bandwidth limited applications. Multiplying a sparse matrix (as well as its transpose in the unsymmetric case) with a dense vector is the core of sparse iterative methods. In this paper, we present a new multithreaded algorithm for the symmetric case which potentially cuts the bandwidth requirements in half while exposing lots of parallelism in practice. We also give a new data structure transformation, called bitmasked register blocks, which promises significant reductions on bandwidth requirements by reducing the number of indexing elements without introducing additional fill-in zeros. Our work shows how to incorporate this transformation into existing parallel algorithms (both symmetric and unsymmetric) without limiting their parallel scalability. Experimental results indicate that the combined benefits of bitmasked register blocks and the new symmetric algorithm can be as high as a factor of 3.5x in multicore performance over an already scalable parallel approach. We also provide a model that accurately predicts the performance of the new methods, showing that even larger performance gains are expected in future multicore systems as current trends (decreasing byte:flop ratio and larger sparse matrices) continue. I.
Keyphrases
sparse matrix-vector multiplication bandwidth requirement sparse matrix register block additional fill-in zero new method unsymmetric case combined benefit current trend parallel scalability core count multicore architecture bitmasked register block flop ratio floating-point performance symmetric case significant reduction future multicore system multicore performance scalable parallel approach new symmetric algorithm performance gain bandwidth limited application parallel algorithm dense vector sparse iterative method new data structure transformation peak memory bandwidth experimental result
