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Data access partitioning for fine-grain parallelism on multicore architectures (2007)
| Venue: | In Proceedings of the 40th Annual IEEE/ACM Symposium on Microarchitecture |
| Citations: | 22 - 0 self |
BibTeX
@INPROCEEDINGS{Chu07dataaccess,
author = {Michael Chu and Rajiv Ravindran and Scott Mahlke},
title = {Data access partitioning for fine-grain parallelism on multicore architectures},
booktitle = {In Proceedings of the 40th Annual IEEE/ACM Symposium on Microarchitecture},
year = {2007}
}
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Abstract
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a single chip requires programmer and compiler intervention to increase the amount of parallel work possible. Much of the recent work has fallen into the areas of coarse-grain parallelization: new programming models and different ways to exploit threads and data-level parallelism. This work focuses on a complementary direction, improving performance through automated fine-grain parallelization. The main difficulty in achieving a performance benefit from fine-grain parallelism is the distribution of data memory accesses across the data caches of each core. Poor choices in the placement of data accesses can lead to increased memory stalls and low resource utilization. We propose a profile-guided method for partitioning memory accesses across distributed data caches. First, a profile determines affinity relationships between memory accesses and working set characteristics of individual memory operations in the program. Next, a program-level partitioning of the memory operations is performed to divide the memory accesses across the data caches. As a result, the data accesses are proactively dispersed to reduce memory stalls and improve computation parallelization. A final detailed partitioning of the computation instructions is performed with knowledge of the cache location of their associated data. Overall, our data partitioning reduces stall cycles by up to 51 % versus data-incognizant partitioning, and has an overall speedup average of 30 % over a single core processor. 1.
Keyphrases
data access fine-grain parallelism multicore architecture data cache memory access computation instruction memory stall versus data-incognizant partitioning performance benefit cache location recent work different way program parallelization new programming model memory operation program-level partitioning complementary direction coarse-grain parallelization computation parallelization data memory access individual memory operation fine-grain parallelization single core processor main difficulty poor choice single chip reduces stall cycle affinity relationship low resource utilization data-level parallelism recent design shift towards final detailed partitioning overall speedup average increased memory stall parallel work significant amount future abundance profile-guided method
