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Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures (2001)
| Venue: | In Proc. of the International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems (IWACT |
| Citations: | 16 - 0 self |
BibTeX
@INPROCEEDINGS{Zalamea01softwareand,
author = {Javier Zalamea and Josep Llosa and Eduard Ayguadé and Mateo Valero},
title = {Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures},
booktitle = {In Proc. of the International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems (IWACT},
year = {2001}
}
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Abstract
High-performance microprocessors are currently designed with the purpose of exploiting the inherent instruction level parallelism (ILP) available in applications. The techniques used in their design and the aggressive scheduling techniques used to exploit this ILP tend to increase the register requirements of the loops. In this paper we overview some hardware and software techniques proposed in the literature to alleviate the high register demands of aggressive scheduling heuristics on VLIW cores. From the software point of view, instruction scheduling can stretch lifetimes and reduce the register pressure. If more registers than those available in the architecture are required, some actions (such as the injection of spill code) have to be applied to reduce this pressure, at the expense of some performance degradation. From the hardware point of view, this degradation could be avoided if a high--capacity register file were included without causing a negative impact on the design of the processor (cycle time, area and power dissipation) . Future scalable VLIW cores will require the use of clustering to decentralize the design and to meet the technology constraints. New aggressive instruction scheduling techniques will be required to minimize the negative effect of this resource clustering and delays to move data around. Keywords--- Modulo scheduling, Register requirements, Spill code, Register file organization, clustered organization. I.
Keyphrases
vliw architecture register file utilization hardware technique register requirement spill code new aggressive instruction software technique instruction scheduling register file organization aggressive scheduling technique software point hardware point power dissipation vliw core high-performance microprocessor negative impact high register demand register pressure future scalable vliw core high capacity register file performance degradation cycle time technology constraint inherent instruction level parallelism negative effect keywords modulo scheduling resource clustering
