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Instruction replication: Reducing delays due to inter-pe communication latency (2003)
| Venue: | In Proc. of the Intl. Conf. on Parallel Architectures and Compilation Techniques |
| Citations: | 11 - 0 self |
BibTeX
@INPROCEEDINGS{Aggarwal03instructionreplication:,
author = {Aneesh Aggarwal},
title = {Instruction replication: Reducing delays due to inter-pe communication latency},
booktitle = {In Proc. of the Intl. Conf. on Parallel Architectures and Compilation Techniques},
year = {2003},
pages = {46--55}
}
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Abstract
As feature sizes are becoming smaller, wire delays are becoming very critical. Clustering is a popular decentralization approach to reduce the impact of shrinking technologies on clock speed. In this approach, the centralized instruction window is replaced with multiple smaller windows, called clusters (PEs). The performance of these clustered processors depends on the amount of inter-PE communication and load imbalance incurred by the distribution algorithm used to distribute instructions among the PEs. In this paper, we investigate a novel approach of reducing the impact of inter-PE communication latency, while preserving good load balance. The basic idea is to selectively replicate instructions in those PEs where their results are required. The replication is done based on heuristics that weigh the potential benefits of replication. We found that with instruction replication, the IPC of a clustered processor is significantly higher than that obtained without instruction replication and is within just 8 % of that of a superscalar configuration with a centralized instruction window.
Keyphrases
instruction replication inter-pe communication latency reducing delay centralized instruction window wire delay potential benefit inter-pe communication superscalar configuration popular decentralization approach feature size load imbalance novel approach basic idea distribution algorithm good load balance clock speed clustered processor
