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Automatic quantification of cache side-channels
| Venue: | IN: PROC. 24TH INTERNATIONAL CONFERENCE ON COMPUTER-AIDED VERIFICATION (CAV |
| Citations: | 18 - 2 self |
BibTeX
@INPROCEEDINGS{Köpf_automaticquantification,
author = {Boris Köpf and Laurent Mauborgne and Martín Ochoa},
title = { Automatic quantification of cache side-channels},
booktitle = {IN: PROC. 24TH INTERNATIONAL CONFERENCE ON COMPUTER-AIDED VERIFICATION (CAV},
year = {},
pages = {564--580},
publisher = {}
}
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Abstract
The latency gap between caches and main memory has been successfully exploited for recovering sensitive input to programs, such as cryptographic keys from implementation of AES and RSA. So far, there are no practical general-purpose countermeasures against this threat. In this paper we propose a novel method for automatically deriving upper bounds on the amount of information about the input that an adversary can extract from a program by observing the CPU’s cache behavior. At the heart of our approach is a novel technique for efficient counting of concretizations of abstract cache states that enables us to connect state-of-the-art techniques for static cache analysis and quantitative information-flow. We implement our counting procedure on top of the AbsInt TimingExplorer, one of the most advanced engines for static cache analysis. We use our tool to perform a case study where we derive upper bounds on the cache leakage of a 128-bit AES executable on an ARM processor with a realistic cache configuration. We also analyze this implementation with a commonly suggested (but until now heuristic) countermeasure applied, obtaining a formal account of the corresponding increase in security.
Keyphrases
automatic quantification cache side-channels static cache analysis upper bound efficient counting main memory novel technique cpu cache behavior state-of-the-art technique sensitive input realistic cache configuration case study absint timingexplorer 128-bit aes executable counting procedure latency gap formal account practical general-purpose countermeasure cryptographic key abstract cache state arm processor corresponding increase advanced engine novel method cache leakage
