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Exploring instruction caching strategies for tightly-coupled shared-memory clusters
| Venue: | in System on Chip (SoC), 2011 International Symposium on |
| Citations: | 2 - 1 self |
BibTeX
@INPROCEEDINGS{Bortolotti_exploringinstruction,
author = {Daniele Bortolotti and Francesco Paterna and Christian Pinto and Andrea Marongiu and Martino Ruggiero and Luca Benini},
title = {Exploring instruction caching strategies for tightly-coupled shared-memory clusters},
booktitle = {in System on Chip (SoC), 2011 International Symposium on},
year = {},
pages = {34--41}
}
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Abstract
Abstract—Several Chip-Multiprocessor designs today leverage tightly-coupled computing clusters as a building block. These clusters consist of a fairly large number N of simple cores, featuring fast communication through a shared multibanked L1 data memory and ≈ 1 Instruction-Per-Cycle (IPC) per core. Thus, aggregated I-fetch bandwidth approaches f ∗ N, where f is the cluster clock frequency. An effective instruction cache architecture is key to support this I-fetch bandwidth. In this paper we compare two main architectures for instruction caching targeting tightly coupled CMP clusters: (i) private instruction caches per core and (ii) shared instruction cache per cluster. We developed a cycle-accurate model of the tightly coupled cluster with several configurable architectural parameters for exploration, plus a programming environment targeted at ef-ficient data-parallel computing. We conduct an in-depth study of the two architectural templates based on the use of both synthetic microbenchmarks and real program workloads. Our results provide useful insights and guidelines for designers. I.
Keyphrases
tightly-coupled shared-memory cluster simple core ef-ficient data-parallel computing abstract several chip-multiprocessor design today real program workload large number i-fetch bandwidth approach i-fetch bandwidth effective instruction cache architecture building block cmp cluster several configurable architectural parameter instruction cache cluster clock frequency synthetic microbenchmarks cycle-accurate model useful insight programming environment main architecture private instruction cache architectural template fast communication multibanked l1 data memory in-depth study
