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## Memory efficient scalable decoder architectures for Low Density Parity Check codes (2006)

### Citations

240 | Urbanke, “Analysis of SumProduct Decoding of Low-Density Parity-Check Codes Using a Gaussian Approximation
- Chung, Richardson, et al.
- 2001
(Show Context)
Citation Context ...iscovered by Gallager [1] have been the focus of intense research in recent years. It has been showed that LDPC codes can be designed to achieve communication at rates close to Shannon capacity limit =-=[2]-=-. Better coding gains and low complexity decoding compared to turbo codes have made them a strong candidate for application in upcoming communication standards. Recently, a number of LDPC decoder arch... |

180 | Low-Density Parity-Check Codes Based on Finite Geometries: A Rediscovery and New Results - Kou, Lin, et al. - 2001 |

154 |
Low-Density Parity Check Codes
- Gallager
- 1963
(Show Context)
Citation Context ...t and latency requirements by scaling the computational units of a serial architecture and partitioning the memory for parallel read and write access. 1 Introduction LDPC codes discovered by Gallager =-=[1]-=- have been the focus of intense research in recent years. It has been showed that LDPC codes can be designed to achieve communication at rates close to Shannon capacity limit [2]. Better coding gains ... |

115 | Quasi-cyclic low-density parity-check codes from circulant permutation matrices
- Fossorier
- 2004
(Show Context)
Citation Context ...osed in our previous work [20]. This procedure has implementation difficulties due to reasons (i) and (ii). Recently, LDPC codes constructed from Circular Permutation Matrices(CPM) have been proposed =-=[25]-=-, [27], [14]. Our architecture uses these family of codes and our heuristic construction procedure works as follows. (i) First construct a base matrix of size n columns and k rows such that the number... |

102 | Reduced-complexity decoding of LDPC codes
- Chen, Dholakia, et al.
- 2005
(Show Context)
Citation Context ...ty algorithms for LDPC decoding have been widely used. Issues related to implementation of Min-Sum algorithm and its modifications were explored by Zhao et al [24], Chenet al [5]. Recently Chen et al =-=[6]-=- have presented the various log-likelihood-ratio-based beliefpropagation decoding algorithms and their reduced complexity derivatives for LDPC codes. The performance and complexity of various reduced ... |

75 |
A reduced complexity decoder architecture via layered decoding of LDPC codes
- Hocevar
(Show Context)
Citation Context ...ly when a large portion of the graph is decoded in parallel. For serial/partly parallel architectures where a small portion of the graph is decoded there would be hardly any memory reduction. Hocevar =-=[23]-=- has also presented a reduced complexity decoder using layered decoding. Our proposed decoder with serial scheduling has faster convergence as presented in [9] and requires lesser memory. Guilloud et ... |

33 | Block-LDPC: A practical LDPC coding system design approach
- Zhong, Zhang
- 2005
(Show Context)
Citation Context ...ructured realization of the decoder was presented in [16]. A joint LDPC code-encoderdecoder design approach called Block-LDPC taking into account hardware-oriented constraints was given by Zang et al =-=[11]-=-. A partly parallel implementation with a joint code-decoder design approach with 56 Mbps throughput was presented in [13]. A parallel decoder architecture with a decoding throughput of 1 Gbps was giv... |

31 | On Implementation of MinSum Algorithm and its Modifications for Decoding Low-Density Parity-Check (LDPC) Codes
- Zhao, Zarkeshvari, et al.
- 2005
(Show Context)
Citation Context ...g the log-tanh function, reduced complexity algorithms for LDPC decoding have been widely used. Issues related to implementation of Min-Sum algorithm and its modifications were explored by Zhao et al =-=[24]-=-, Chenet al [5]. Recently Chen et al [6] have presented the various log-likelihood-ratio-based beliefpropagation decoding algorithms and their reduced complexity derivatives for LDPC codes. The perfor... |

30 | Lamda-Min Decoding Algorithm of Regular and Irregular
- Guilloud, Boutillon, et al.
- 2003
(Show Context)
Citation Context ...s also presented a reduced complexity decoder using layered decoding. Our proposed decoder with serial scheduling has faster convergence as presented in [9] and requires lesser memory. Guilloud et al =-=[4]-=- presented an offset min-sum decoding algorithm offering a tradeoff between performance and complexity to save extrinsic message memory. Our proposed architecture scheduling requires lesser memory com... |

30 | High throughput low-density parity-check decoder architectures
- Yeo, Pakzad, et al.
(Show Context)
Citation Context ...a time was presented in [8]. A staggered decoding schedule which uses an approximation of belief propagation and requires memory dependant on the number of bits in the codeword was given by Yeo et al =-=[17]-=-. The staggered schedule suffers a coding loss compared to SPA and is suitable only for less than five decoding iterations. An hierarchial formulation of LDPC code that allows a structured realization... |

23 | On finite précision implementation of low density parity check codes décoder", The 2001
- Zhang, Wang, et al.
- 2001
(Show Context)
Citation Context ... studied by Ping and Leung [15]. A parity likelihood function was proposed to improve performance. The effects of finite word length on log-BP based SPA decoding was previously studied by Zhang et al =-=[12]-=-. Non-uniform quantization was proposed for extrinsic values with both ψ and ψ −1 functions implemented using the same look up tables. The authors limit the range of LLR values between 0 and 4 and con... |

20 |
An FPGA and ASIC Implementation of Rate 1/2 8088-b Irregular Low Density Parity Check Decoder
- Chen, Hocevar
- 2003
(Show Context)
Citation Context ...parallel decoder architecture with a decoding throughput of 1 Gbps was give by Blanksby and Howland [18]. A partly parallel decoder architecture for irregular LDPC codes was given by Chen and Hocevar =-=[22]-=-. Code design and parallelization concepts were explained in the paper. An LDPC decoding schedule for memory access reduction was presented in [21]. While most of the above references implement the SP... |

19 | Decoding low density parity check codes with finite quantization bits
- Ping, Leung
- 2000
(Show Context)
Citation Context ...enting Lch, Lb, Lc and ψ values offers a trade-off between performance and hardware requirements of the decoder. Finite precision performance of SPA in its original form was studied by Ping and Leung =-=[15]-=-. A parity likelihood function was proposed to improve performance. The effects of finite word length on log-BP based SPA decoding was previously studied by Zhang et al [12]. Non-uniform quantization ... |

19 | Semi-parallel reconfigurable architectures for real-time LDPC decoding - Karkooti, Cavallaro |

14 | Optimized message passing schedules for LDPC decoding
- Radosavljevic, Baynast, et al.
- 2005
(Show Context)
Citation Context ...he scheduling used for update procedure. In normal parallel/flooding scheduling all the bit-node updates are completed before making any check-node updates and vice versa. In layered/turbo scheduling =-=[30]-=-, [23], [26], [9] only a set of bit-node updates are done and the newly formed Lb messages are used for a set of check-node updates. Now the newly formed Lc messages are used in another set of bit-nod... |

13 | Approximate-min* constraint node updating for LDPC code decoding
- Jones, Valles, et al.
- 2003
(Show Context)
Citation Context ... modified SPA algorithm allows intrinsic feedback of soft values at the check update unit. This proposed modification is similar to the ApproximateMin Constraint independently proposed by Jones et al =-=[3]-=- but we implement the approximation in log-tanh domain rather than implementing directly on the LLR values based on the Jacobian logarithmic identity. Also no specific decoder architecture has been pr... |

13 |
Decoding Architecture for Array-code-based LDPC Codes
- Olcer
(Show Context)
Citation Context ...previous work [20]. This procedure has implementation difficulties due to reasons (i) and (ii). Recently, LDPC codes constructed from Circular Permutation Matrices(CPM) have been proposed [25], [27], =-=[14]-=-. Our architecture uses these family of codes and our heuristic construction procedure works as follows. (i) First construct a base matrix of size n columns and k rows such that the number of 1 ′ s in... |

12 | Two-dimensional correction for min-sum decoding of irregular LDPC codes
- Zhang, Fossorier, et al.
- 2006
(Show Context)
Citation Context ...is overestimation [5], [6], [24]. The correction factor depends on the rate of the code and also an irregular code would need different correction factors for bit and check nodes of different degrees =-=[7]-=-. Hence when the same hardware is used for decoding codes of various rates and different degree profiles the finite precision requirements for the various correction factors is not well understood. 4.... |

11 |
Memory-efficient sum-product decoding of LDPC codes
- Sankar, Narayanan
- 2004
(Show Context)
Citation Context ...ages and architectures proposed in [22], [21] which store either check to bit or bit to check messages. Memory efficient turbo decoding algorithms were proposed by Mansour et al [9] and Shankar et al =-=[10]-=-. Such a decoding architecture uses layered decoding approach to save memory and the approach adopted in [9] requires lesser number of iterations as the decoder converges faster compared to regular 2 ... |

8 |
Low-Density Parity-Check Code Constructions for Hardware Implementation
- Liao, Yeo, et al.
- 2004
(Show Context)
Citation Context ...a coding loss compared to SPA and is suitable only for less than five decoding iterations. An hierarchial formulation of LDPC code that allows a structured realization of the decoder was presented in =-=[16]-=-. A joint LDPC code-encoderdecoder design approach called Block-LDPC taking into account hardware-oriented constraints was given by Zang et al [11]. A partly parallel implementation with a joint code-... |

8 | A memory efficient serial LDPC decoder architecture
- Prabhakar, Narayanan
- 2005
(Show Context)
Citation Context ...ini |Lb(i)|. Then M2(j) is given by, M2(j) = M1 − ψ(L q−1 b (j)) M2(i) = M1 for all other edges(i �= j) (14) This intrinsic feedback for the magnitude of Lc messages was previously presented by us in =-=[34]-=- and similar to the Approximate-Min check update [3] but differs in implementation to suit our check update procedure which is done in parallel with finding the least reliable edge as explained in sec... |

7 |
VLSI Implementation of Encoder and Decoder for Low-Density Parity-Check Codes
- Sivakumar
- 2001
(Show Context)
Citation Context ...cations to meet coding, throughput, latency, decoder area and power requirements. A serial decoder architecture that uses regular SPA decoding algorithm and decodes one bit at a time was presented in =-=[8]-=-. A staggered decoding schedule which uses an approximation of belief propagation and requires memory dependant on the number of bits in the codeword was given by Yeo et al [17]. The staggered schedul... |

7 |
High-rate low-density parity check codes based on anti-Pasch affine geometries
- Vasic
(Show Context)
Citation Context ...n our previous work [20]. This procedure has implementation difficulties due to reasons (i) and (ii). Recently, LDPC codes constructed from Circular Permutation Matrices(CPM) have been proposed [25], =-=[27]-=-, [14]. Our architecture uses these family of codes and our heuristic construction procedure works as follows. (i) First construct a base matrix of size n columns and k rows such that the number of 1 ... |

6 |
FPGA based implementation of decoder for array low-density parity-check codes
- Bhagawat, Uppal, et al.
- 2005
(Show Context)
Citation Context ...given by (⌊ S×M P ×t ⌋ + 1). Array codes [14] are highly structured and the shift between adjacent blocks in a row or column is a constant. This property of constant shift difference has been used in =-=[29]-=- to eliminate the need for cyclic shifters. Similar structured parity check matrices can be formed in our above mentioned procedure if we can choose the shift on adjacent permutation blocks in a row o... |

3 |
Memory efficient turbo decoder architecture for LDPC codes
- Mansour, Shanbhag
(Show Context)
Citation Context ... and check to bit messages and architectures proposed in [22], [21] which store either check to bit or bit to check messages. Memory efficient turbo decoding algorithms were proposed by Mansour et al =-=[9]-=- and Shankar et al [10]. Such a decoding architecture uses layered decoding approach to save memory and the approach adopted in [9] requires lesser number of iterations as the decoder converges faster... |

3 |
A massively scalable architecture for low-density parity-check codes
- Selvarathinam, Choi, et al.
- 2003
(Show Context)
Citation Context ...he decoder and the scheduling used. A random bit filling procedure for constructing the parity check matrix taking into consideration the parallelization constraints was proposed in our previous work =-=[20]-=-. This procedure has implementation difficulties due to reasons (i) and (ii). Recently, LDPC codes constructed from Circular Permutation Matrices(CPM) have been proposed [25], [27], [14]. Our architec... |

2 |
An LDPC decoding shedule for memory access reduction
- Gunnam, Choi, et al.
- 2004
(Show Context)
Citation Context ...r irregular LDPC codes was given by Chen and Hocevar [22]. Code design and parallelization concepts were explained in the paper. An LDPC decoding schedule for memory access reduction was presented in =-=[21]-=-. While most of the above references implement the SPA decoding algorithm using the log-tanh function, reduced complexity algorithms for LDPC decoding have been widely used. Issues related to implemen... |

1 |
Near optimum universal beleif propagation based decoding of lowdensity parity check codes
- Chen, Fossorier
- 2002
(Show Context)
Citation Context ...unction, reduced complexity algorithms for LDPC decoding have been widely used. Issues related to implementation of Min-Sum algorithm and its modifications were explored by Zhao et al [24], Chenet al =-=[5]-=-. Recently Chen et al [6] have presented the various log-likelihood-ratio-based beliefpropagation decoding algorithms and their reduced complexity derivatives for LDPC codes. The performance and compl... |

1 |
A 609-mW 1-Gb/s 1024-b, rate 1/2 low density parity-check code decoder
- Blanksby, Howland
(Show Context)
Citation Context ...entation with a joint code-decoder design approach with 56 Mbps throughput was presented in [13]. A parallel decoder architecture with a decoding throughput of 1 Gbps was give by Blanksby and Howland =-=[18]-=-. A partly parallel decoder architecture for irregular LDPC codes was given by Chen and Hocevar [22]. Code design and parallelization concepts were explained in the paper. An LDPC decoding schedule fo... |

1 |
An efficient message passing shedule for LDPC decoding
- Sharon, Litsyn, et al.
(Show Context)
Citation Context ...g used for update procedure. In normal parallel/flooding scheduling all the bit-node updates are completed before making any check-node updates and vice versa. In layered/turbo scheduling [30], [23], =-=[26]-=-, [9] only a set of bit-node updates are done and the newly formed Lb messages are used for a set of check-node updates. Now the newly formed Lc messages are used in another set of bit-node updates an... |

1 | Designing LDPC codes using cyclic shifts - Okumora |

1 |
Designing LDPC codes with bitfilling
- Campello, Modha, et al.
- 2001
(Show Context)
Citation Context ...ve near shannon capacity for an AWGN channel [2]. Once the profile polynomials are known the connection between a bit and check node is made at random with constraints to avoid cycles of short length =-=[32]-=-. Random construction is not suitable for hardware implementation due to the following reasons. (i)The bit and check node connection for each edge has to be stored at the decoder. (ii) Random connecti... |