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... difference of these two counters to determine when there are no more readers in the system). This is state-of-the-art RW Lock implementation for Intel platform. MCS-Lock Michael and Scott’s MCS Lock =-=[16]-=-. We present two standard synthetic microbenchmarks: a Red-Black Tree and a single location counter (Counter-1). 0.00E+00 2.00E+03 4.00E+03 6.00E+03 8.00E+03 1.00E+04 1.20E+04 1 2 4 6 8 10 12 14 16 18...

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...rrency, but then again, read-write locks offer none. All past STM algorithms (see [21]), including the TinySTM algorithm of Felber, Fetzer, and Reigel [17] and the TL2 STM of Dice, Shalev, and Shavit =-=[9]-=-, are optimistic or partially optimistic: some transactions can run into inconsistencies and be forced to abort and retry. Welc et al. [5] introduced the notion of irrevocable transactions. Their syst...

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...ng mechanism so that it will first try to signal write transactions from the same chip so as to get better locality of reference in consecutive critical section executions and avoid NUMA traffic (See =-=[11]-=-). We defined a constant threshold value that will limit the number of signals in the same chip, in order to avoid starvation. As a reference point, we also compared our algorithms to the TL2 STM on t...

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...revalent in many applications, to proceed in parallel with one another. However, read-write locks do not offer any parallelism between reads and writes. In a ground breaking paper, Rajwar and Goodman =-=[18]-=- proposed speculative lockelision (SLE), the automatic replacement of locks by optimistic hardware transactions, with the hope that the transactions will not abort due to contention, and not fail to e...

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...d consistency mechanism in the style of the TL2 algorithm of Dice, Shalev, and Shavit [9]. The range of shared memory is divided into stripes, each with an associated local version-number (similar to =-=[9, 17, 1]-=-), initialized to 0. We use a shared global version number (as introduced by [9, 22]). The global version and stripe versions are 64bit unsigned integers. Every transaction reads the global version up...

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...calls. It provides only limited write-write concurrency, but then again, read-write locks offer none. All past STM algorithms (see [21]), including the TinySTM algorithm of Felber, Fetzer, and Reigel =-=[17]-=- and the TL2 STM of Dice, Shalev, and Shavit [9], are optimistic or partially optimistic: some transactions can run into inconsistencies and be forced to abort and retry. Welc et al. [5] introduced th...

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...e transactions sequentially in a manner similar to [5], yet allows concurrent wait-free read-only transactions without using read-locks or multiple versions as in [10, 7]. We do so by using a TL2/LSA =-=[9, 22]-=- style time-stamping scheme (we can reduce the time-stamp to two bits) together with a new variation on the quiescence array mechanism of Matveev and Shavit [2]. The almost sequential execution of the...

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..., and Reigel [17] and the TL2 STM of Dice, Shalev, and Shavit [9], are optimistic or partially optimistic: some transactions can run into inconsistencies and be forced to abort and retry. Welc et al. =-=[5]-=- introduced the notion of irrevocable transactions. Their system was the first to answer the need to execute systems calls within transactions, but did not relieve the programmer from having to plan a...

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...urrency even for contended code and even if the code includes system calls. It provides only limited write-write concurrency, but then again, read-write locks offer none. All past STM algorithms (see =-=[21]-=-), including the TinySTM algorithm of Felber, Fetzer, and Reigel [17] and the TL2 STM of Dice, Shalev, and Shavit [9], are optimistic or partially optimistic: some transactions can run into inconsiste...

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...lement the synchronization between the write and read transactions we use a variant of the quiescence array mechanism of Matveev and Shavit [2] (which in turn is based on epoch mechanisms such as RCU =-=[8]-=-). Read transactions are made wait-free: locations being updated by a concurrent write transaction (there is only one such transaction at a time) are read from a logged value, and otherwise are read d...

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...ecute systems calls within transactions, but did not relieve the programmer from having to plan and be aware of which operations to run within the specialized pessimistic transaction. Perelman et al. =-=[7]-=- showed a partially pessimistic STM that can support read-only transactions by keeping multiple versions of the transactions’ view during its execution. Attiya and Hillel [10] presented a partially pe...

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...-write parallelism that does not appear in locks. However, if transactions do fail, SLE defaults to using the original lock which has no write-read parallelism. A few years ago, Roy, Hand, and Harris =-=[4]-=- proposed an all software implementation of SLE, in which transactions are executed speculatively in software, and when they fail, or if they cannot be executed due to system calls, the system default...

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...nsaction. Perelman et al. [7] showed a partially pessimistic STM that can support read-only transactions by keeping multiple versions of the transactions’ view during its execution. Attiya and Hillel =-=[10]-=- presented a partially pessimistic STM that provides read-only transactions without multiple versions. However, their solution requires acquiring a read-lock for every location being read. Our new ful...

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...10, 7]. We do so by using a TL2/LSA [9, 22] style time-stamping scheme (we can reduce the time-stamp to two bits) together with a new variation on the quiescence array mechanism of Matveev and Shavit =-=[2]-=-. The almost sequential execution of the pessimistic write transactions is a drawback relative to standard TL2, but also has some interesting performance advantages. The most important one is that our...

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...s. However, their solution requires acquiring a read-lock for every location being read. Our new fully pessimistic STM design is an encounter-time variation of our earlier commit-time pessimistic STM =-=[3]-=-. Our algorithm executes write transactions sequentially in a manner similar to [5], yet allows concurrent wait-free read-only transactions without using read-locks or multiple versions as in [10, 7]....

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... Locks We present three ways in which PLE can be used to implement lock-elision: nonspeculative software-only lock elision, as a fall back (slow path) for the HLE (e.g., Intel’s hardware lock-elision =-=[12]-=-), and as a fall back using optimistic hardware TM (e.g., Intel’s restricted transactional memory RTM [12]). 3.1 Non-speculative Software Lock-Elision To perform non-speculative elision, for every RW-...