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## Parametric Circuit Representation Using Inductive Boolean Functions (1993)

Venue: | In Computer Aided Verification, CAV '93, LNCS 697 |

Citations: | 17 - 2 self |

### Citations

3524 | Graph-based algorithms for boolean function manipulation
- Bryant
- 1986
(Show Context)
Citation Context ...or implied, of the U.S. government. On the other hand, verification of non-parametric circuits has been successfully performed by various techniques based on symbolic manipulationof Boolean functions =-=[1, 4, 5, 6, 8, 10, 11, 18]-=-. The success of these techniques is largely due to the availability of automatic symbolic Boolean manipulation algorithms (using canonical Boolean function representations) that are efficient in prac... |

504 | Efficient implementation of a BDD package.
- Brace, Rudell, et al.
- 1991
(Show Context)
Citation Context ... success of these techniques is largely due to the availability of automatic symbolic Boolean manipulation algorithms (using canonical Boolean function representations) that are efficient in practice =-=[3, 4]-=-. There have been some recent efforts in applying these techniques for iterative systems [19], but unlike our approach, they use automata-based methods. The primary motivation for our verification met... |

425 |
A Computational Logic Handbook.
- Boyer, Moore
- 1988
(Show Context)
Citation Context ...-theoretic frameworks. Note that we do not claim to address the general problem of induction in a first-order (or higher-order) logic setting, as is done in theorem-proving systems with formal logics =-=[2, 7]-=-. 1.2 Overview Our verification methodology based on symbolic IBF manipulation can be naturally described in terms of the following components: -- characterization of useful classes of IBFs, and a rep... |

332 |
Symbolic model checking: 10 states and beyond
- Burch, Clarke, et al.
- 1992
(Show Context)
Citation Context ...or implied, of the U.S. government. On the other hand, verification of non-parametric circuits has been successfully performed by various techniques based on symbolic manipulationof Boolean functions =-=[1, 4, 5, 6, 8, 10, 11, 18]-=-. The success of these techniques is largely due to the availability of automatic symbolic Boolean manipulation algorithms (using canonical Boolean function representations) that are efficient in prac... |

113 | A structural induction theorem for processes
- Kurshan, McMillan
- 1989
(Show Context)
Citation Context ...ous verification work with parametric descriptions of circuits includes reasoning by induction both in theorem-proving systems [7, 13, 16, 20], and within model checking/languagecontainment paradigms =-=[9, 17, 21]-=- (an extended bibliography can be found in a recent survey [14]). The main advantage with these approaches is that a single proof serves to establish the functional or behavioral correctness of an ent... |

106 |
Formal Hardware Verification Methods: a Survey. Formal Methods
- Gupta
- 1992
(Show Context)
Citation Context ...s reasoning by induction both in theorem-proving systems [7, 13, 16, 20], and within model checking/languagecontainment paradigms [9, 17, 21] (an extended bibliography can be found in a recent survey =-=[14]-=-). The main advantage with these approaches is that a single proof serves to establish the functional or behavioral correctness of an entire family of circuits. However, most available approaches are ... |

104 | Verification of the futurebus+ cache coherence protocol
- Clarke, Grumberg, et al.
- 1993
(Show Context)
Citation Context ...or implied, of the U.S. government. On the other hand, verification of non-parametric circuits has been successfully performed by various techniques based on symbolic manipulationof Boolean functions =-=[1, 4, 5, 6, 8, 10, 11, 18]-=-. The success of these techniques is largely due to the availability of automatic symbolic Boolean manipulation algorithms (using canonical Boolean function representations) that are efficient in prac... |

103 | Verifying properties of large sets of processes with network invariants
- Wolper, Lovinfosse
- 1989
(Show Context)
Citation Context ...ous verification work with parametric descriptions of circuits includes reasoning by induction both in theorem-proving systems [7, 13, 16, 20], and within model checking/languagecontainment paradigms =-=[9, 17, 21]-=- (an extended bibliography can be found in a recent survey [14]). The main advantage with these approaches is that a single proof serves to establish the functional or behavioral correctness of an ent... |

61 |
Verifying temporal properties of sequential machines without building their state diagrams
- Coudert, Madre, et al.
- 1990
(Show Context)
Citation Context |

60 | Microprocessor design verification
- Hunt
- 1989
(Show Context)
Citation Context ...kground description of our verification methodology. 1.1 Motivation Previous verification work with parametric descriptions of circuits includes reasoning by induction both in theorem-proving systems =-=[7, 13, 16, 20]-=-, and within model checking/languagecontainment paradigms [9, 17, 21] (an extended bibliography can be found in a recent survey [14]). The main advantage with these approaches is that a single proof s... |

58 |
Avoiding the state explosion problem in temporal logic model checking.
- Clarke, Grumber
- 1987
(Show Context)
Citation Context ...ous verification work with parametric descriptions of circuits includes reasoning by induction both in theorem-proving systems [7, 13, 16, 20], and within model checking/languagecontainment paradigms =-=[9, 17, 21]-=- (an extended bibliography can be found in a recent survey [14]). The main advantage with these approaches is that a single proof serves to establish the functional or behavioral correctness of an ent... |

38 | A methodology for hardware verification based on logic simulation,”
- Bryant
- 1991
(Show Context)
Citation Context |

36 |
Hardware verification using higher-order logic.
- Camillieri, Gordon, et al.
- 1986
(Show Context)
Citation Context ...kground description of our verification methodology. 1.1 Motivation Previous verification work with parametric descriptions of circuits includes reasoning by induction both in theorem-proving systems =-=[7, 13, 16, 20]-=-, and within model checking/languagecontainment paradigms [9, 17, 21] (an extended bibliography can be found in a recent survey [14]). The main advantage with these approaches is that a single proof s... |

31 |
Formal verification of the Encore Gigamax cache consistency protocol
- McMillan, Schwalbe
- 1991
(Show Context)
Citation Context |

21 |
Verification of synchronous sequential machines using symbolic execution
- Coudert, Berthet, et al.
- 1989
(Show Context)
Citation Context |

11 |
Formal verification of parameterized hardware designs
- German, Wang
- 1985
(Show Context)
Citation Context ...kground description of our verification methodology. 1.1 Motivation Previous verification work with parametric descriptions of circuits includes reasoning by induction both in theorem-proving systems =-=[7, 13, 16, 20]-=-, and within model checking/languagecontainment paradigms [9, 17, 21] (an extended bibliography can be found in a recent survey [14]). The main advantage with these approaches is that a single proof s... |

5 |
Correctness proofs of parameterized hardware modules in the Cathedral-II synthesis environment
- Verkest, Johannes, et al.
- 1990
(Show Context)
Citation Context |

4 |
Inductive verification of iterative systems
- Rho, Somenzi
- 1992
(Show Context)
Citation Context ...anipulation algorithms (using canonical Boolean function representations) that are efficient in practice [3, 4]. There have been some recent efforts in applying these techniques for iterative systems =-=[19]-=-, but unlike our approach, they use automata-based methods. The primary motivation for our verification methodology was to combine reasoning by induction and symbolic tautology-checking in a way that ... |

2 |
de Geus. High level design: A design vision for the 90's
- J
- 1992
(Show Context)
Citation Context ...rms of size parameters. Since reuse of existing designs has become an important issue in practice, use of parametric designs in the form of standard libraries has been emphasized as an emerging trend =-=[12]-=-. By directly addressing the issue of parameterization in our approach, as described in this paper, we provide the necessary framework for representation and verification of such designs. To provide a... |

2 |
Representation and manipulation of inductive Boolean functions
- Gupta, Fisher
- 1992
(Show Context)
Citation Context ...sentations. The schemata details for the two classes of IBFs we have identified so far --- linearly inductive functions (LIFs), and exponentially inductive functions (EIFs) --- can be found elsewhere =-=[15]-=-, and are summarized for convenience in Section 2. The main focus of this paper is on representation of parametric circuits in the form of LIFs and EIFs. The emphasis is on general mechanisms addressi... |

1 |
Automatic verification of synchronouscircuits using symbolic simulation and temporal logic
- Fisher
- 1990
(Show Context)
Citation Context |