Reconfigurable Computing: A Survey of Systems and Software

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Reconfigurable Computing: A Survey of Systems and Software (2000)

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by Katherine Compton , Scott Hauck

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258 - 5 self

Citations

404	Garp: A MIPS Processor with A Reconfigurable Coprocessor. - Hauser, Wawrzynek - 1997
322	VPR: A new packing, placement and routing tool for FPGA research. In: - Betz, Rose - 1997
287	Field-Programmable Gate Arrays”, - Brown, Francis, et al. - 1992
190	The Chimaera Reconfigurable Functional Unit", - Hauck, Fry, et al. - 1997
135	Piperench: A reconfigurable architecture and compiler,” - Goldstein, Schmit, et al. - 2000
134	The Roles of FPGAs in Reprogrammable Systems,” - Hauck - 1998
130	JHDL- an HDL for reconfigurable systems.” - Bellows, Hutchings - 1998
105	Rapid - reconfigurable pipelined datapath,” - Ebeling, Cronquist, et al. - 1996
102	Splash 2. - Arnold, Buell, et al. - 1992
92	The Garp architecture and C compiler - Callahan, Hauser, et al. - 2000
85	Virtual wires: Overcoming pin limitations in FPGA-based logic emulators - Babb, Tessier, et al. - 1993
82	A Detailed Router for Field-Programmable Gate Arrays,” - Brown, Rose, et al. - 1992
81	Napa C: Compiling for a Hybrid RISC/FPGA Architecture”,In - Gokhale, Stone - 1998
80	The Transmogrifier C hardware description language and compiler for FPGAs - Galloway - 1995
70	Balancing interconnect and computation in a reconfigurable computing array (or, why you don’t really want 100% LUT utilization - DeHon - 1999
68	Configuration prefetch for single context reconfigurable coprocessors. - Hauck - 1998
61	Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution - Cong, Wu, et al.
59	New performance-driven FPGA routing algorithms”, - Alexander, Robins - 1995
55	FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density”, - Betz, Rose
51	Fast module mapping and placement for datapaths in FPGAs - Callahan, Chong, et al. - 1998
51	Specifying and Compiling Applications for RaPiD”, In - Cronquist, Franklin, et al. - 1998
51	DPGA Utilization and Application, - DeHon - 1996
48	Parallelizing applications into silicon - Babb, Rinard, et al. - 1999
47	The Design of an SRAM-Based Field-Programmable Gate Array, Part I: Architecture,” - Chow, Seo, et al. - 1999
47	A CAD suite for high-performance FPGA design - Hutchings, Bellows, et al. - 1999
42	Managing pipeline-reconfigurable FPGAs,” - Cadambi, Weener, et al. - 1998
41	Configuration compression for the Xilinx XC6200 FPGA - Hauck, Zhiyuan, et al. - 1998
41	ConCISe: A compiler-driven CPLD-based instruction set accelerator - Kastrup, Bink, et al. - 1999
37	Fast Compilation for Pipelined Reconfigurable Fabrics. - Budiu, Goldstein - 1999
31	Partitioning sequential circuits on dynamically reconfigurable FPGAs,” - Marek-Sadowska - 1999
31	Technology mapping for FPGAs with embedded memory blocks,” - Cong, Xu - 1998
31	Configuration compression for FPGA-based embedded systems,” - Dandalis, Prasanna - 2005
30	Configuration relocation and defragmentation for run-time reconfigurable computing,” - Compton, Li, et al. - 2002
27	Parallel Processing in a Restructurable Computer System - Estrin, Bussel, et al. - 1963
27	A case study of partially evaluated hardware circuits: Keyspecific DES - Leonard, Magione-Smith - 1997
25	Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks - Gokhale, Stone - 1999
25	Technology mapping for TLU FPGA’s based on decomposition of binary decision diagrams - Chang, Marek-Sadowska, et al. - 1996
24	Routing Architectures for Hierarchical Field Programmable Gate Arrays - Agarwal, Lewis - 1994
24	PCI-PipeRench and the SwordAPI: A System for Stream-based Reconfigurable - Laufer, Taylor, et al. - 1999
23	Run-Time Compaction of FPGA Designs - Diessel, ElGindy - 1997
23	Macro-Based Hardware Compilation of Java Bytecodes into a Dynamic Reconfigurable Computing System - Cardoso, Neto - 1999
23	Dynamic reconfiguration to support concurrent applications - Jean, Tomko, et al. - 1999
22	Hierarchical Interconnection Structures for Field Programmable Gate Arrays - Lai, Wang - 1997
21	CPR: a configuration profiling tool - Cadambi, Goldstein - 1999
21	Multi-FPGA Systems - Hauck - 1995
21	Object Oriented Circuit-Generators in Java - Chu, Weaver, et al. - 1998
20	The Trianus System and Its Application to Custom Computing - Gehring, Ludwig - 1996
19	Configuration Compression for the Xilinx XC6200 - Hauck, Li, et al. - 1998
18	Software Technologies for Reconfigurable Systems - Hauck, Agarwal - 1996
18	C.; Mesh routing topologies for multi-FPGA systems - Hauck, Ebeling
18	Hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems [C - Khalid - 1998
17	Fast integrated tools for circuit design with FPGAs - Gehring, Ludwig - 1998
17	A reliable lz data compressor on reconfigurable coprocessors,” - Huang, Saxena, et al. - 2000
16	An Operating System for Custom Computing Machines based on the Xputer Paradigm - Kress, Hartenstein, et al. - 1997
15	An FPGA Implementation and Performance Evaluation of the Serpent Block Cipher. - Elbirt, Paar - 2000
15	Runlength compression techniques for fpga configuration - S, Wilson - 1999
14	Acceleration of an FPGA router - Chan, Schlag - 1997
14	Pin assignment for multi-FPGA systems - Hauck, Borriello - 1997
13	A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable for Embedding - Haynes, Cheung - 1998
12	A methodology for fast FPGA floorplanning - Emmert, Bhatia - 1999
12	A performance and routability-driven router for FPGA’s considering path delays,” - Lee, Wu - 1997
10	Method of Using Electronically Reconfigurable Logic Circuits - Butts, Batcheller - 1991
10	Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation - Cong, Hwang - 1998
10	Hybrid Product Term and LUT Based Architectures Using Embedded Memory - Heile, Leaver - 1999
10	Logic synthesis for field-programmable gate arrays,” - Hwang, Owens, et al. - 1994
10	Use of Genetic Algorithm - SpillmanR, Nelson, et al. - 1993
10	Routing Architecture and Layout Synthesis for Multi-FPGA Systems [D - Khalid - 1999
9	Using Cone Structures for Circuit Partitioning into FPGA Packages - Brasen, Saucier - 1998
9	Safe and protected execution for the morph/AMRM reconfigurable processor - Chien, Byun - 1999
9	Object oriented circuitgenerators - CHU, WEAVER, et al. - 1998
9	An efficient algorithm for performance-optimal FPGA technology mapping with retiming - Cong, Wu - 1998
9	Configuration caching vs. data caching for striped FPGAs - Deshpande, Somani, et al. - 1999
9	Exploiting reconfigurability through domain-specific systems - HUTCHINGS - 1997
9	VirtualWires: A technology for massive multiFPGA systems - Agarwal - 1994
9	Cut Ranking and Pruning: Enabling A General And Efficient - Cong, Wu, et al. - 1999
9	Synthesis and Floorplanning For Large Hierarchical FPGAs - Krupnova, Rabedaoro, et al. - 1997
9	Don’t Care Discovery for FPGA - Li, Hauck - 1999
8	Runlength Compression Techniques for FPGA - Hauck, Wilson - 1999
8	Configuration Caching for FPGAs - Li, Compton, et al. - 2000
7	Multiterminal net routing for partial crossbar-based multi-FPGA systems - EJNIOUI, RANGANATHAN - 1999
7	Fast Module Mapping and Placement for Datapaths - Callahan, Chong, et al. - 1998
6	Genetic algorithms in software and in hardware—a performance analysis of workstation and custom computing machine implementations - Graham, Nelson - 1996
6	A Representation for Dynamic Graphs in Reconfigurable Hardware and its Application to Fundamental Graph Algorithms. - Huelsbergen - 2000
6	Input-driven partitioning methods and application to synthesis on table-lookupbased FPGA’s - ABOUZEID, BABBA, et al. - 1993
6	A Methodology for Fast FPGA - Emmert, Bhatia - 1999
6	Automatic Allocation of Arrays to Memories - Gokhale, Stone - 1999
5	Factoring Large Numbers with Programmable Hardware (Presentation) UCLA Electrical Engineering Dept. kimmer,billms@icsl.ucla.edu http://klabs.org/richcontent/MAPLDCon99/Presentations/D5A_ Kim_S.PDF - Kim, Mangione-Smith
4	An hardware/software partitioning algorithm for custom computing machines - CHICHKOV, ALMEIDA - 1997
4	Emmanouelides, “Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation - Dollas, Sotiriades, et al. - 1998
4	Technology mapping of heterogeneous LUT-based FPGAs - INUANI, SAUL - 1997
3	Macro-based hardware compilation of JavaTM bytecodes into a dynamic reconfigurable computing system - Cardoso, Neto - 1999
3	General modeling and technology-mapping technique for LUT-based FPGAs - CHOWDHARY, HAYES - 1997
3	Configuration Relocation and Defragmentation for FPGAs”, Northwestern University Technical Report, Available online at http://www.ece.nwu.edu/~kati/publications.html - Compton, Cooley, et al. - 2000
3	Automatic mapping of algorithms onto multiple FPGASRAM Modules. Field-Programmable Logic and Applications - ACOCK, DIMOND - 1997
3	Acceleration of an FPGA - Chan, Schlag - 1997
3	Safe and Protected Execution for the Morph/AMRM - Chien, Byun - 1999
3	and C.Ebeling, "Mesh Routing Topologies for Multi-FPGA systems - Hauck, Borriello - 1998
3	Technology mapping of LUT based FPGAs for delay optimisation - LIN, DAGLESS, et al. - 1997
2	Reconfigurable Computing 205 - BURNS, DONLIN, et al. - 1997
1	Emmanouelides, "Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation - Dollas, Sotiriades, et al. - 1998