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... fig. 1(a)) have to change in synchrony; input queues have to be organized per-output (VOQ - virtual output queues); and the crossbar scheduler has to solve a bipartite graph matching problem [1] [2] =-=[3]-=-. Synchronous operation introduces at least two overheads: (i) variable-size packets have to be segmented into fixed-size cells before entering the crossbar; and (ii) cells entering a crossbar chip th...

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...gnals in fig. 1(a)) have to change in synchrony; input queues have to be organized per-output (VOQ - virtual output queues); and the crossbar scheduler has to solve a bipartite graph matching problem =-=[1]-=- [2] [3]. Synchronous operation introduces at least two overheads: (i) variable-size packets have to be segmented into fixed-size cells before entering the crossbar; and (ii) cells entering a crossbar...

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...e weighted fair queueing (WFQ) quality of service (QoS) [4]. To cope with the segmentation overhead and the scheduler inefficiencies of unbuffered crossbars, switches and routers use internal speedup =-=[5]-=- –often by a factor of two to three in commercial products. 1 This speedup is very expensive: today, the crossbar chip power consumption is often the limiting factor for the aggregate performance of t...

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...ly, the loosely-coupled input and output schedulers are able to find very efficient long-term solutions to the crossbar scheduling problem, with capability for advanced QoS, without requiring speedup =-=[6]-=- [7] [8] [9] [10]. These facts allow significant cost reductions, since they eliminate the need for speedup and egress buffering. 2 Although advantageous, the buffered crossbar architecture was not ve...

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...ressure between them (figures 10-13). Recently, with the availability of technology for single-chip buffered crossbars, a number of groups studied fixed-size-cell buffered crossbars –see e.g. [7] [8] =-=[13]-=- and our previous work [9] [10]; from industry, a representative example is [14]. This paper differs from the above in that we consider buffered crossbars directly operating on variable-size packets. ...

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...s in fig. 1(a)) have to change in synchrony; input queues have to be organized per-output (VOQ - virtual output queues); and the crossbar scheduler has to solve a bipartite graph matching problem [1] =-=[2]-=- [3]. Synchronous operation introduces at least two overheads: (i) variable-size packets have to be segmented into fixed-size cells before entering the crossbar; and (ii) cells entering a crossbar chi...

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...loosely-coupled input and output schedulers are able to find very efficient long-term solutions to the crossbar scheduling problem, with capability for advanced QoS, without requiring speedup [6] [7] =-=[8]-=- [9] [10]. These facts allow significant cost reductions, since they eliminate the need for speedup and egress buffering. 2 Although advantageous, the buffered crossbar architecture was not very popul...

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... crossbar proposals date at least as far back as 1987: Nojima e.a. [11] described a “bus matrix” switch with buffers only at the crosspoints (no input buffers), operating on variable-size packets; we =-=[12]-=- proposed a switch with small crosspoint buffers, large input buffers, and backpressure between them (figures 10-13). Recently, with the availability of technology for single-chip buffered crossbars, ...

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...the loosely-coupled input and output schedulers are able to find very efficient long-term solutions to the crossbar scheduling problem, with capability for advanced QoS, without requiring speedup [6] =-=[7]-=- [8] [9] [10]. These facts allow significant cost reductions, since they eliminate the need for speedup and egress buffering. 2 Although advantageous, the buffered crossbar architecture was not very p...

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...sbars directly operating on variable-size packets. To the best of our knowledge, there have been only two previous studies on this topic: (i) Stephens and Zhang [6]; and (ii) Yoshigoe and Christensen =-=[15]-=- [16]. Our present work differs from these studies in the following ways. Firstly, we consider the hardware implementation of such crossbars: section 3 discusses a number of issues and gives cost esti...

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...ut and quality of service (QoS) guarantees; this coupled with the overhead due to packet segmentation2 brings the need for internal speed-up 3 - usually a factor of two to four to commercial products =-=[4]-=-. Second, the segmentation at inputs brings the need for reassembly at outputs, which requires significant egress buffering (CIOQ - Combined Input-Output Queuing). On the other hand, buffered crossbar...

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...ogy for single-chip buffered crossbars, a number of groups studied fixed-size-cell buffered crossbars –see e.g. [7] [8] [13] and our previous work [9] [10]; from industry, a representative example is =-=[14]-=-. This paper differs from the above in that we consider buffered crossbars directly operating on variable-size packets. To the best of our knowledge, there have been only two previous studies on this ...

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...ely-coupled input and output schedulers are able to find very efficient long-term solutions to the crossbar scheduling problem, with capability for advanced QoS, without requiring speedup [6] [7] [8] =-=[9]-=- [10]. These facts allow significant cost reductions, since they eliminate the need for speedup and egress buffering. 2 Although advantageous, the buffered crossbar architecture was not very popular i...

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...or performance of buffered crossbars without speedup relative to unbuffered ones with considerable speedup. 2. PREVIOUS WORK Buffered crossbar proposals date at least as far back as 1987: Nojima e.a. =-=[11]-=- described a “bus matrix” switch with buffers only at the crosspoints (no input buffers), operating on variable-size packets; we [12] proposed a switch with small crosspoint buffers, large input buffe...

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... directly operating on variable-size packets. To the best of our knowledge, there have been only two previous studies on this topic: (i) Stephens and Zhang [6]; and (ii) Yoshigoe and Christensen [15] =-=[16]-=-. Our present work differs from these studies in the following ways. Firstly, we consider the hardware implementation of such crossbars: section 3 discusses a number of issues and gives cost estimates...

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...op R new packet ack inc counter packet data In wrData wr wrAddr 2−port SRAM rd rdData to w outmux (a) Clock domains, (b) crosspoint logic rdAddr counter inc ClockOut domain ClockIn d. companion paper =-=[17]-=- does consider that topic at great depth (also refer to [18]). 3. INTERNAL ORGANIZATION AND COST We discuss implementation issues for variable-packet-size buffered crossbars, and we estimate the silic...

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...) when the cell time is short, they cannot practically achieve both high throughput and low latency; and (ii) it is very hard for them to provide weighted fair queueing (WFQ) quality of service (QoS) =-=[4]-=-. To cope with the segmentation overhead and the scheduler inefficiencies of unbuffered crossbars, switches and routers use internal speedup [5] –often by a factor of two to three in commercial produc...

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...he iSLIP switch, all flows’ performance degrades considerably due to the absense of any flow control. The corresponding diagrams are not shown here, due to space limitations, but they can be found in =-=[30]-=-, along with information regarding the simulation environment. 3) Throughput Experiment: Next, we experiment with unbalanced traffic (i.e. non-uniform destinations), considering an unbalance factor f,...

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...coupled input and output schedulers are able to find very efficient long-term solutions to the crossbar scheduling problem, with capability for advanced QoS, without requiring speedup [6] [7] [8] [9] =-=[10]-=-. These facts allow significant cost reductions, since they eliminate the need for speedup and egress buffering. 2 Although advantageous, the buffered crossbar architecture was not very popular in pro...

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...assume that credits are transmitted on dedicated links, as shown in figure 2(a) –not by time-sharing the packetout links leading to the line cards– because our experience from the ATLAS I switch chip =-=[22]-=- showed that this greatly simplifies the design. The average load on a credit link cannot exceed one credit per minimum-size packet time; however, credits can be generated at up to 32 times higher rat...

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...int(); //for debugging purpose }; We assume that the schedulers at input and output ports operate in accordance to a specified finite state machine. For the description of that state machine refer to =-=[11]-=-. Statistics monitor is the module that collects the statistics for the simulation. It computes the packets’ average/max delay, the delay’s standard deviation, the switch throughput, as well as when t...

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..., 114ns; output scheduling time, similarly, 30ns; credit propagation time, similarly, 114 ns; credit transmission time, 32ns. For additional information on design issues and on the simulator refer to =-=[18]-=-. We model variable-size packet arrivals at the input ports, using mostly two distinct traffic patterns: PoisPar, poisson process arrivals with packet sizes that follow the bounded pareto distribution...

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...e bulk transactions such as FTP transfers or HTTP page responses. The duration of a session generated by IG and BG follows the pareto distribution with mean value 125 packets and 8 Kbyte respectively =-=[28]-=-. All sessions are delimited by an idle period and they are generated according to a Poisson process. Packets within IG sessions vary from 40 to 44 bytes and their interarrival time follows the expone...

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...nthBackb. Under uniform traffic, the destination port of each session is chosen uniformly; all packets in a session have the same destination port. For the hotspot traffic, we follow the methology in =-=[19]-=-: each destination belonging to a designated set of “hotspots” receives traffic at 100% collective output utilization (percentage) 1 0.95 0.9 0.85 0.8 0.75 0.7 1500 1600 1700 RTT250_wc RTT300_wc RTT35...

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... line card FIFO queue for multiplexing Fig. 4. Basic Traffic Generator. The aggregate load of a pair of sources is 100Mbps. For M × 100Mbps load we multiplex M pairs. minimum packet transmission time =-=[27]-=- 4 . Credits destined to the same input line-card are sent in FIFO order. The RTT between input line-cards and switch fabric has been set to 500 byte times (corresponding to 400 ns at 10 Gbps line rat...