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## A Methodology for Hardware Verification Based on Logic Simulation (1991)

Venue: | Journal of the ACM |

Citations: | 38 - 4 self |

### Citations

1751 | An Axiomatic Basis for Computer Programming
- Hoare
- 1969
(Show Context)
Citation Context ...chieve this goal, assertions about the state variables and how they are transformed by the input values are expressed in a notation similar to the Floyd-Hoare assertion method of program verification =-=[9, 13]-=-. Each assertion is then verified by a short simulation sequence. At the present stage of this research, we require the user to prove manually that the set of assertions forms a complete system specif... |

737 |
Assigning meanings to programs
- Floyd
(Show Context)
Citation Context ...chieve this goal, assertions about the state variables and how they are transformed by the input values are expressed in a notation similar to the Floyd-Hoare assertion method of program verification =-=[9, 13]-=-. Each assertion is then verified by a short simulation sequence. At the present stage of this research, we require the user to prove manually that the set of assertions forms a complete system specif... |

470 |
Representation of events in nerve nets and finite automata
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- 1956
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Citation Context ... ff) for any ff 2 BI k and any q 1 ; q 2 2 Q. A specification is definite when it is k-definite for some k. Otherwise it is indefinite. This class of sequential systems was first identified by Kleene =-=[15]-=-. Since that time, various definitions have appeared, viewing sequential systems either as recognizers [21] or transducers [16]. Our definition most closely matches that of Kohavi [16]. However, he de... |

340 |
Switching and Finite Automata Theory.
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- 1970
(Show Context)
Citation Context ...hat X represents an unknown or ambiguous digital value. It is shown that the style of simulation required to prove correctness must depend on the nature of the system specification. A definite system =-=[16, 21], for whic-=-h the behavior depends on only a bounded number of previous inputs, can be verified by straightforward "blackbox " simulation. Black-box simulation involves simply observing the output produ... |

124 | Algebraic Structure Theory of Sequential Machines - Hartmanis, RE - 1966 |

101 |
The Design and Analysis of VLSI Circuits.
- Glasser, Dobberpulh
- 1985
(Show Context)
Citation Context ...depends on its operating environment. As an example, the direction of information flow through a cmos transmission gate is determined solely by the driving capabilities of the circuitry at either end =-=[11]-=-. Clearly, any specification of such a gate must include restrictions on the environment in which it is placed. As a notable exception to these highly simplified models, Weise [25, 26] has developed a... |

86 |
Gedanken-experiments on sequential machines. Automata study, Annals of mathematics studies
- Moore
- 1956
(Show Context)
Citation Context ...e it. 1.3. Overview of the Methodology The task of evaluating a circuit by simulating its response to a set of stimuli relates closely to the "machine identification" problem first described=-= by Moore [20]-=-. He showed that, in general, no finite set of stimuli could fully characterize the behavior of a sequential system. He suggested overcoming this problem by fixing an upper bound on the total number o... |

84 | Automatic verification of sequential circuits using temporal logic
- Browne, Clarke, et al.
- 1986
(Show Context)
Citation Context ...he caveat that circuits are assumed to operate on synchronized input data. Asynchronous systems seems to call for more powerful class of verification tools, such as the model checker of Clarke, et al =-=[3, 8]-=-, since they cannot be viewed simply as processing a single sequence of input data. This research provides two major contributions to the state of the art in circuit validation. First, it presents a s... |

68 |
A Switch-Level Model and Simulator for MOS Digital Systems”,
- Bryant
- 1984
(Show Context)
Citation Context ...nts a nor logic gate. Figure 1 shows two proposed implementations in cmos technology [11]. If we were to simulate these circuits using a simulator that can model a mos circuit at the transistor level =-=[4]-=-, the following responses would be produced when the input patterns are applied in the 6 sequence shown: a b out 1 out 2 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 0 The two circuits appear identical for all possi... |

52 |
Hierarchical verification of asynchronous circuits using temporal logic
- Clarke, Mishra
- 1985
(Show Context)
Citation Context ...he caveat that circuits are assumed to operate on synchronized input data. Asynchronous systems seems to call for more powerful class of verification tools, such as the model checker of Clarke, et al =-=[3, 8]-=-, since they cannot be viewed simply as processing a single sequence of input data. This research provides two major contributions to the state of the art in circuit validation. First, it presents a s... |

26 |
The theory of definite automata
- Perles, Rabin, et al.
- 1962
(Show Context)
Citation Context ...hat X represents an unknown or ambiguous digital value. It is shown that the style of simulation required to prove correctness must depend on the nature of the system specification. A definite system =-=[16, 21], for whic-=-h the behavior depends on only a bounded number of previous inputs, can be verified by straightforward "blackbox " simulation. Black-box simulation involves simply observing the output produ... |

20 |
Applications of Ternary Algebra to the Study of Static Hazards",
- Yoeli, Rinon
- 1964
(Show Context)
Citation Context ...ssume that the user can issue Erase commands, causing all state variables to be set to X. Although the power of three-valued simulation has been studied extensively in the context of hazard detection =-=[7, 17, 27]-=-, its potential role in circuit verification has not been widely recognized. In the interest of generality and simplicity, the paper views hardware specification, digital circuits, and logic simulatio... |

17 | On a Ternary Model of Gate Networks,
- Brzozowski, Yoeli
- 1979
(Show Context)
Citation Context ...ssume that the user can issue Erase commands, causing all state variables to be set to X. Although the power of three-valued simulation has been studied extensively in the context of hazard detection =-=[7, 17, 27]-=-, its potential role in circuit verification has not been widely recognized. In the interest of generality and simplicity, the paper views hardware specification, digital circuits, and logic simulatio... |

14 |
VERIFY: A Program for Proving Correctness of Digital Hardware Designs,"
- Barrow
- 1984
(Show Context)
Citation Context ...at the level of confidence it provides is only as strong as the degree to which the abstract model matches actual system operation. 1.1. Structural Approaches Most hardware verification methodologies =-=[1, 2, 18, 19, 23, 24, 25, 26]-=- utilize structural techniques. In such an approach, the circuit is described hierarchically, where a component is defined at one level in the hierarchy as an interconnection of components defined at ... |

13 | Symbolic verification of MOS circuits
- Bryant
- 1985
(Show Context)
Citation Context ... be applied to a circuit, all of which might be relevant to the values of the outputs. For these cases, we propose symbolic simulation to reduce the number of patterns simulated. A symbolic simulator =-=[5]-=- resembles a conventional logic simulator, except that the input sequences can contain Boolean variables in addition to the constants 1 and 0. During simulation the values of the circuit state and out... |

13 |
CIRCAL: A calculus for circuit description
- Milne
(Show Context)
Citation Context ...at the level of confidence it provides is only as strong as the degree to which the abstract model matches actual system operation. 1.1. Structural Approaches Most hardware verification methodologies =-=[1, 2, 18, 19, 23, 24, 25, 26]-=- utilize structural techniques. In such an approach, the circuit is described hierarchically, where a component is defined at one level in the hierarchy as an interconnection of components defined at ... |

11 |
Proving the Correctness of Digital Hardware Designs,"
- Barrow, G
- 1983
(Show Context)
Citation Context ...at the level of confidence it provides is only as strong as the degree to which the abstract model matches actual system operation. 1.1. Structural Approaches Most hardware verification methodologies =-=[1, 2, 18, 19, 23, 24, 25, 26]-=- utilize structural techniques. In such an approach, the circuit is described hierarchically, where a component is defined at one level in the hierarchy as an interconnection of components defined at ... |

11 |
Formal verification of parameterized hardware designs
- German, Wang
- 1985
(Show Context)
Citation Context ... Many large, but highly structured circuits have been verified structurally. Second, they can be extended to parameterized circuit descriptions, proving the correctness of entire families of circuits =-=[10]-=-. Finally, structural verifiers can apply different modeling abstractions according to the level in the hierarchy, such as representing signals at lower levels as bits and at higher levels as integers... |

8 | Verifying a Static RAM Design by Logic Simulation
- Bryant
- 1988
(Show Context)
Citation Context ...nd it. Despite these extensions to the notation, the underlying principle remains that of state transition simulation. This verification methodology has successfully been applied to a 4096-bit memory =-=[6]-=-. This circuit holds n = 2 m bits, where each memory cell i, such that 0si ! n, consists of a feedback path containing electrical nodes b i and b i along with a pair of access transistors [11]. As a s... |

8 |
A three-level design verification system
- Jephson, McQuarrie, et al.
- 1969
(Show Context)
Citation Context ...the behavior over a three-valued domain with conventional Boolean values 0 and 1, plus a value X representing an undefined or uninitialized signal. Such a capability is found in most logic simulators =-=[14]-=-. In addition to supplying input patterns during simulation, we assume that the user can issue Erase commands, causing all state variables to be set to X. Although the power of three-valued simulation... |

3 |
An analysis of ternary simulation as a tool for race detection
- Lengauer, Näher
- 1986
(Show Context)
Citation Context ...ssume that the user can issue Erase commands, causing all state variables to be set to X. Although the power of three-valued simulation has been studied extensively in the context of hazard detection =-=[7, 17, 27]-=-, its potential role in circuit verification has not been widely recognized. In the interest of generality and simplicity, the paper views hardware specification, digital circuits, and logic simulatio... |

3 |
Verification of VLSI designs
- Shostak
- 1983
(Show Context)
Citation Context |

3 |
Hardware Verification
- Wagner
- 1977
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Citation Context |

2 |
A model for hardware description and verification
- Milne
- 1984
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Citation Context |

2 |
Automatic Formal Verification of Synchronous MOS VLSI Designs
- Weise
- 1986
(Show Context)
Citation Context |

1 |
A switch-level model and simulator for M O S digital systems
- Bryant
- 1984
(Show Context)
Citation Context ...ents a NOR logic gate.sFigure 1 shows two proposed implementations in CMOS technology [10]. If we were tossimulate these circuits using a simulator that can model a MOS circuit at the transistorslevel=-=[4]-=-, the following responses would be produced when the input patterns are appliedsin the sequence shown:s6sIncorrect CorrectsB BsFigure 1: Implementations of a N O R Gate in CMOSsA B OUTi O U T 2s0 0 1 ... |

1 |
Verification of VLSI designs. Proceedings of the Third Caltech Conference on
- Roth, Testing, et al.
- 1980
(Show Context)
Citation Context ...edsby setting each element appearing in a literal to its specified value, and all other elementssto X. This vector is analogous to the cubical representation of a product term in a Booleansexpression =-=[20]-=-.sP r o p o s i t i o n 4 For convex predicate P{u) and vector a G Bny P(a) if and only if up < a.sProof: First, assume that P{a) holds. For the vectors to be ordered uP ^ a, there mustsbe at least on... |