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... bandwidth requirements are forcing siliconsvendors to provide HSSIs with higher speeds. In 2002, theshighest data rate in Altera FPGAs was only 1.25 Gbps perschannel, available in its Mecury devices =-=[3]-=-; now in AlterasStratix IV GT FPGAs, the rate has increased to 11.3 Gbpssper channel, with up to 48 HSSIs on each device [4].sAnother FPGA provider, Xilinx, provides up to thirty-sixs11.2 Gbps HSSIs i...

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...ttersand receiver jitter tolerance. Jitter is the deviation of a signalsfrom its ideal timing that may cause bit errors. Total Jitter (TJ)sconsists of Deterministic Jitter (DJ) and Random Jitter (RJ)s=-=[21]-=-. Many HSSI standards define jitter performance at thesBER level of 10-12, which requires running at least 1013 bits.sThis requirement fundamentally limits test speed:sforsinstance, at 3Gbps, it takes...

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...and the degree of integration,sit is challenging to design fault-free electronic products. Assa consequence, close to 25% of all design resources at Intelsare now spent on post-fabrication validation =-=[9]-=-. It isschallenging and expensive to qualify the HSSI devices,sespecially the jitter performance, including transmitter jittersand receiver jitter tolerance. Jitter is the deviation of a signalsfrom i...

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... and increase thesintegration, many signal integrity related issues arise, suchsas timing jitter, noise and frequency loss. A few keystechnologies have been developed recently to address thesesissues =-=[1]-=-. Pre-emphasis and equalization techniques aresused to compensate frequency-related losses, especiallysthose related to Printed Circuit Board (PCB) design due tosskin effect and dielectric loss. Pre-e...

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...sspecification 800mVpp.sFigure 12. The Tx output waveform after the delay linesFigure 13 plots the extracted DJ profile from the captured datassignal using the Tx jitter extraction scheme proposed in =-=[11]-=-.sAs we can see, the DJ profile is close to a square waveform,swhich is the profile of the jitter source we injected to the datassignal. There is minor distortion at the second half of the highslevel,...

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...fy design parameters, such as Tx jitter andsRx jitter tolerance. Recently, there was some research thatsused DFT features or special modules to verify designsparameters through external loopback [14] =-=[15]-=-. Oursapproach does not rely on any DFT features or specialsinstruments; it only needs a few extra components that cansfit into a testing loadboard. The approach is especiallysattractive for multiple-...

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...lips forsthe purpose of demonstrating the BERT functionalities. Thes8B10B encoder encodes the 8-bit sequences to 10-bitssequences to ensure enough bit transitions in the serial data forsdate recovery =-=[17]-=-. A FIFO is used to ensure that there issalways data ready for transmission after the testing begins.sComma words are inserted at the start of the testing for wordsalignment. The 8B10B Decoder recover...

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...: RingsOscillator (RO) and LC tank oscillator (LC tank). RO hassthe advantages of small chip area and wide tunablesfrequency range, but LC tanks provide lower noise andsbetter jitter performance [6], =-=[7]-=-. Multiple data rates can besimplemented by changing divider ratios inside the PLL orsby providing additional VCOs. In Altera Stratix IV GTsFPGAs, the RO can support data rates from 600Mbps tos10.3 Gb...

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...os10.3 Gbps; two LC tanks are also implemented in thissdevice, one with 4.9~6.375 Gbps optimized for PCIe/CEI-6scompliance and the other with 9.9~11.3 Gbps optimized forsXLAUI/CAUI/CEI-11G compliance =-=[8]-=-.sA side-effect of implementing multiple data rates is that thesjitter performance of the HSSI can vary across the datasrange. If the same PLL is used at multiple speeds, such as 6sGbps and 8.5Gbps, o...

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...one.s3. ATE-based ApproachessATE is traditionally used in production testing. Due to its highsthroughput, there is a trend in recently years to also use ATEsto facilitate validation and debugging. In =-=[10]-=-, we propose ans115 Authorized licensed use limited to: McGill University. Downloaded on November 27, 2009 at 00:19 from IEEE Xplore.sRestrictions apply.saccelerated Rx jitter tolerance testing and va...

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...te orstest the whole Tx.s3.2 Rx Testing SolutionsFor Rx validation and testing, jitter tolerance is the mostschallenging. Firstly we need test signals with controllablesamounts of injected jitter. In =-=[13]-=-, we propose a scheme tosinject controllable amount of PJ though the AWG on ATE. Bys116 Authorized licensed use limited to: McGill University. Downloaded on November 27, 2009 at 00:19 from IEEE Xplore...

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...Control Figure 9. Block diagram of the BERTsTo overcome these limitations, we explore FPGA-basedsapproaches. To detect the bit errors in HSSIs, we can re-usesthe FPGA-based parallel BERT presented in =-=[16]-=-. Figure 9sshows the block diagram of the BERT.sA Pseudo-RandomsBit Sequence (PRBS) and a k-1 bits Pseudo-Random WordsSequence (PRWS) form a pattern generator, where k is theswidth of the parallel dat...

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...arator that transitioned the delay line output when thesramp generator reached a certain voltage level. Moressophisticated delay lines then were developed using asvoltage-controlled delay line (VCDL) =-=[18]-=-.sToday, ultra wideband phase delay lines have beensdeveloped using the InGap or InP Heterostructure BipolarsTransistor (HBT). InGap HBT is a proven reliablestechnology that has been widely used in la...