Arijit Raychowdhury edit

Affiliation School of Electrical and Computer Engineering, Purdue University
Publications 22
H-index 5
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Publications

#Cited
24 2004) “Circuit-Compatible Model of Ballistic Carbon Nanotube Field- Effect Transistors” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - of ISTE Dr.V.Kannan was born in Ariyalore, Tamil nadu, India in 1970. He received his Bachelor Degree in Electronics and Communication Engineering from Madurai Kamarajar University in the year1991, Masters Degree in Electronics and control from BITS, Pila
16 A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies - in VLSI Design”, Proc. Of the International Workshop on Computational Electronics (IWCE - 2004
14 Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling - DAC
7 A Novel Delay Fault Testing Methodology Using On-Chip Low-Overhead Delay Measurement Hardware at Strategic - Probe Points, ETS, 2005. Proceedings of the 14th Asian Test Symposium (ATS ’05) 1081-7735/05 $20.00 © 2005 IEEE
6 A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application - Proc. Design, Automation and Test in Europe - 2005
5 Computing with subthreshold leakage: Device/circuit/architecture co-design for ultralow-power subthreshold operation - IEEE Trans. Very Large S. I. Syst. 2005
2 Multi-junction fault-tolerance Architecture for Nanoscale Crossbar Memories - IEEE Transactions on Nanotechnology - 2008
1 Modelling hysteresis in vanadium dioxide oscillators -
1 Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement - in Nanoscale SRAM, Test Symposium, 2005. Proceedings. 14th Asian - 2005
1 Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current -
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor -
Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis -
Responsible Editor: A. D. Singh - - 2006
Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles – Ad-vanced -
11.1 Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling* -
3.2 Device Optimization for Ultra-Low Power Digital Sub-Threshold Operation -
1Modeling and Simulation of Vanadium dioxide Relaxation Oscillators -
Pairwise Coupled Hybrid Vanadium Dioxide-MOSFET (HVFET) Oscillators for Non-Boolean Associative Computing -
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current∗,† - - 2003
Modeling and Estimation of Total Leakage in Scaled CMOS Logic Circuits By -

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