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12
Automatic derivation of timing constraints by failure analysis
 In Proc. International Conference on Computer Aided Verification
, 2002
"... Abstract. This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly. A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. Each veri ..."
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Abstract. This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly. A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. Each verification run performs timed state space enumeration under the given delay bounds, and produces a failure trace if it exists. The failure trace is analyzed, and sufficient timing constraints to prevent the failure is obtained. Then, the delay bounds are tightened according to the timing constraints by using an ILP (Integer Linear Programming) solver. This process terminates when either some delay bounds under which no failure is detected are found or no new delay bounds to prevent the failures can be obtained. The experimental results using a naive implementation show that the proposed method can efficiently handle asynchronous benchmark circuits and nontrivial GasP circuits.
Correctness and Reduction in Timed Circuit Analysis
, 2002
"... To increase performance, circuit designers are experimenting with timed circuits  a class of circuits that rely on a complex set of timing constraints for correct functionality. This is evidenced in published experimental designs from industry. Timing constraints are key to the success of these de ..."
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Cited by 9 (1 self)
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To increase performance, circuit designers are experimenting with timed circuits  a class of circuits that rely on a complex set of timing constraints for correct functionality. This is evidenced in published experimental designs from industry. Timing constraints are key to the success of these designs, and algorithms to verify timing constraints are required to make them practical in commercial applications. Due to the complexity of the constraints, however, traditional static timing analysis is not adequate. Timed state space analysis is required; thus, improved timed state space analysis is paramount to producing efficient timed circuits. This diss
Improved POSET timing analysis in Timed Petri Nets
 in Proceedings of International Workshop on Synthesis and System Integration of Mixed Technologies
, 2001
"... Abstract—This paper presents an improved timing algorithm for the analysis of timed Petri nets that is based on the POSET algorithm. The new algorithm reduces the number of redundant concurrent orderings the POSET algorithm explores by directly considering causal assignments. This paper shows that t ..."
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Abstract—This paper presents an improved timing algorithm for the analysis of timed Petri nets that is based on the POSET algorithm. The new algorithm reduces the number of redundant concurrent orderings the POSET algorithm explores by directly considering causal assignments. This paper shows that the new algorithm, when compared to the original POSET algorithm, results in an average 2.25 times improvement in runtime and a 57 % reduction in stored zones when applied to a suite of example circuits. Although the new algorithm can suffer an exponential increase in the number of causal assignments it must consider, this paper shows it to be a property of the POSET algorithm itself that does not happen often in practice. I.
Framework of Timed Trace Theoretic Verification Revisited
 TIT CS TECHNICAL REPORT
, 2001
"... This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarc ..."
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Cited by 4 (1 self)
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This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.
Partial order reduction for detecting safety and timing failures of timed circuits
 IEICE Trans. Inf. & Syst
, 2005
"... Abstract. This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original ..."
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Abstract. This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original untimed trace theory. Consequently, its conformance checking supports hierarchical verification. Experimenting with the STARI circuits, the proposed approach shows its effectiveness. 1
BRUTUS: A Model Checker for Security Protocols
 Process Capability, Release 3.0, Bell Canada Acquisitions
, 2001
"... representing the oÆcial policies, either expressed or implied, of the MPO, NSF, SRC, the U.S. government or any other entity. ..."
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representing the oÆcial policies, either expressed or implied, of the MPO, NSF, SRC, the U.S. government or any other entity.
1 Stochastic Semantics and Statistical Model Checking for Networks of Priced Timed Automata
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Compositional Behavior Modeling and Formal Validation of Canal System Operations with Finite State Automata
"... Isr develops, applies and teaches advanced methodologies of design and analysis to solve complex, hierarchical, heterogeneous and dynamic problems of engineering technology and systems for industry and government. ..."
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Isr develops, applies and teaches advanced methodologies of design and analysis to solve complex, hierarchical, heterogeneous and dynamic problems of engineering technology and systems for industry and government.
Model Checking Control Communication of a FACTS Device
"... This paper concerns the design and verification of a realtime communication protocol for sensor data collection and processing between an embedded computer and a DSP. In such systems, a certain amount of data loss without recovery may be tolerated. The key issue is to define and verify the correctne ..."
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This paper concerns the design and verification of a realtime communication protocol for sensor data collection and processing between an embedded computer and a DSP. In such systems, a certain amount of data loss without recovery may be tolerated. The key issue is to define and verify the correctness in the presence of these lost data frames under realtime constraints. This paper describes a temporal verification that if the end processes do not detect that too many frames are lost, defined by comparison of error counters against given threshold values, then there will be a bounded delay between transmission of data frames and reception of control frames. This verification and others presented herein were performed with the model checkers SPIN and RTSPIN. Keywords:modelchecking, verification, realtime, lossy, control,