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27
Verification of Asynchronous Circuits using Timed Automata
"... In this work we apply the timing verification tool OpenKronos, which is based on timed automata, to verify correctness of numerous asynchronous circuits. The desired behavior of these circuits is specified in terms of signal transition graphs (STG) and we check whether the synthesized circuits behav ..."
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Cited by 28 (4 self)
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In this work we apply the timing verification tool OpenKronos, which is based on timed automata, to verify correctness of numerous asynchronous circuits. The desired behavior of these circuits is specified in terms of signal transition graphs (STG) and we check whether the synthesized circuits behave correctly under the assumption that the inputs satisfy the STG conventions and that the gate delays are bounded between two given numbers. Our results demonstrate the viability of the timed automaton approach for timing analysis of certain classes of circuits.
Automatic derivation of timing constraints by failure analysis
 In Proc. International Conference on Computer Aided Verification
, 2002
"... Abstract. This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly. A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. Each veri ..."
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Cited by 12 (0 self)
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Abstract. This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly. A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. Each verification run performs timed state space enumeration under the given delay bounds, and produces a failure trace if it exists. The failure trace is analyzed, and sufficient timing constraints to prevent the failure is obtained. Then, the delay bounds are tightened according to the timing constraints by using an ILP (Integer Linear Programming) solver. This process terminates when either some delay bounds under which no failure is detected are found or no new delay bounds to prevent the failures can be obtained. The experimental results using a naive implementation show that the proposed method can efficiently handle asynchronous benchmark circuits and nontrivial GasP circuits.
Partial order reduction for verification of timed systems
, 1999
"... conclusions or recommendations expressed in this material are those of the author and do not necessarily reflect the views of SRC, NSF, DARPA, or the United States Government. ..."
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conclusions or recommendations expressed in this material are those of the author and do not necessarily reflect the views of SRC, NSF, DARPA, or the United States Government.
Lazy Transition Systems and Asynchronous Circuit Synthesis With Relative Timing Assumptions
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 2002
"... This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a tran ..."
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Cited by 10 (5 self)
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This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. Lazy transition
Improved POSET timing analysis in Timed Petri Nets
 in Proceedings of International Workshop on Synthesis and System Integration of Mixed Technologies
, 2001
"... Abstract—This paper presents an improved timing algorithm for the analysis of timed Petri nets that is based on the POSET algorithm. The new algorithm reduces the number of redundant concurrent orderings the POSET algorithm explores by directly considering causal assignments. This paper shows that t ..."
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Cited by 9 (8 self)
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Abstract—This paper presents an improved timing algorithm for the analysis of timed Petri nets that is based on the POSET algorithm. The new algorithm reduces the number of redundant concurrent orderings the POSET algorithm explores by directly considering causal assignments. This paper shows that the new algorithm, when compared to the original POSET algorithm, results in an average 2.25 times improvement in runtime and a 57 % reduction in stored zones when applied to a suite of example circuits. Although the new algorithm can suffer an exponential increase in the number of causal assignments it must consider, this paper shows it to be a property of the POSET algorithm itself that does not happen often in practice. I.
On Timing Analysis of Combinational Circuits
 In FORMATS’03, LNCS 2791
, 2003
"... Abstract. In this paper we report some progress in applying timed automata technology to largescale problems. We focus on the problem of finding maximal stabilization time for combinational circuits whose inputs change only once and hence they can be modeled using acyclic timed automata. We develop ..."
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Cited by 9 (1 self)
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Abstract. In this paper we report some progress in applying timed automata technology to largescale problems. We focus on the problem of finding maximal stabilization time for combinational circuits whose inputs change only once and hence they can be modeled using acyclic timed automata. We develop a “divideandconquer” methodology based on decomposing the circuit into subcircuits and using timed automata analysis tools to build conservative lowcomplexity approximations of the subcircuits to be used as inputs for the rest of the system. Some preliminary results of this methodology are reported. 1
Correctness and Reduction in Timed Circuit Analysis
, 2002
"... To increase performance, circuit designers are experimenting with timed circuits  a class of circuits that rely on a complex set of timing constraints for correct functionality. This is evidenced in published experimental designs from industry. Timing constraints are key to the success of these de ..."
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Cited by 9 (1 self)
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To increase performance, circuit designers are experimenting with timed circuits  a class of circuits that rely on a complex set of timing constraints for correct functionality. This is evidenced in published experimental designs from industry. Timing constraints are key to the success of these designs, and algorithms to verify timing constraints are required to make them practical in commercial applications. Due to the complexity of the constraints, however, traditional static timing analysis is not adequate. Timed state space analysis is required; thus, improved timed state space analysis is paramount to producing efficient timed circuits. This diss
Automated analysis of timing information in UML diagrams
 IN: PROCEEDINGS OF THE NINETEENTH IEEE INTERNATIONAL CONFERENCE ON AUTOMATED SOFTWARE ENGINEERING (ASE04
, 2004
"... This paper introduces an approach to adding timing information to UML diagrams for modeling embedded systems. In order to perform automated formal analysis of these UML diagrams with timing information, we extend a previously developed UML formalization framework to provide Promela semantics for th ..."
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Cited by 6 (6 self)
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This paper introduces an approach to adding timing information to UML diagrams for modeling embedded systems. In order to perform automated formal analysis of these UML diagrams with timing information, we extend a previously developed UML formalization framework to provide Promela semantics for the timing elements of the UML diagrams. The paper describes the application of our approach to an electronically controlled steering system obtained from one of our industrial collaborators.
An Extension of the Inverse Method to Probabilistic Timed Automata
, 2009
"... Probabilistic timed automata can be used to model systems in which probabilistic and timing behavior coexist. Verification of probabilistic timed automata models is generally performed with regard to a single reference valuation of the timing parameters. Given such a parameter valuation, we present ..."
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Cited by 5 (3 self)
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Probabilistic timed automata can be used to model systems in which probabilistic and timing behavior coexist. Verification of probabilistic timed automata models is generally performed with regard to a single reference valuation of the timing parameters. Given such a parameter valuation, we present a method for obtaining automatically a constraint on timing parameters for which the reachability probabilities (1) remain invariant and (2) are equal to the reachability probabilities for the reference valuation. The method relies on parametric analysis of a nonprobabilistic version of the probabilistic timed automata model using the “inverse method”. Our approach is useful for avoiding repeated executions of probabilistic model checking analyses for the same model with different parameter valuations. We provide examples of the application of our technique to models of randomized protocols.
Model Checking for Probabilistic Timed Systems
 In Validation of Stochastic Systems – A Guide to Current Research, volume 2925 of LNCS
, 2004
"... Application areas such as multimedia equipment, communication protocols and networks often feature systems which exhibit both probabilistic and timed behaviour. In this paper, we consider analysis of such probabilistic timed systems using the technique of model checking, in which it is verified ..."
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Application areas such as multimedia equipment, communication protocols and networks often feature systems which exhibit both probabilistic and timed behaviour. In this paper, we consider analysis of such probabilistic timed systems using the technique of model checking, in which it is verified automatically whether a system satisfies a certain desired property. In order to describe formally probabilistic timed systems, we consider probabilistic extensions of timed automata, such as realtime probabilistic processes, probabilistic timed automata and continuous probabilistic timed automata, the underlying semantics of each of which is an infinitestate structure. For each formalism, we consider how the wellknown region equivalence relation can be used to reduce the infinite statespace model into a finitestate system, which can then be used for model checking.