In this paper, we propose a Dynamically Reconfigurable Pro-cessor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully pa-rameterized. By specifying architectural parameters, it can automatically generate RTL model, simulation environment, and finally chip layout. In our DRPA generator, although the fundamental design of a processing element (PE) and an inter-PE connection is fixed, the array size, PE granularity, and connection flexibilities of intra/inter PE are selectable. In this paper, we have generated various types of DRPAs and evaluated semiconductor area and speed by using the AS-PLA/STARC 90-nm CMOS technology. From evaluation results, fundamental trade-offs between architectural param-eters and area/delay are analyzed. 1.