The ever increasing complexity of signal processing appli-cations and the desire to reduce the time to market demands efficient compilation techniques for programmable Digital Signal Processors (DSPs). Because the instruction sets of VLIW processors are more regular and orthogonal then the instruction sets of the traditional DSPs, they tend to be more compiler friendly. However in order to improve the maximal clock frequency, the power efficiency and the code density, several register files are used in the newer genera-tion of VLIW processors instead of just one large register file. The use of several register files and partial connected networks leads, for example, to the problem that a result stored in a register file can not be accessed by all the func-tional units in the processor. This makes the assignment of