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Lineartime compression of boundedgenus graphs into informationtheoretically optimal number of bits
 In: 13th Symposium on Discrete Algorithms (SODA
, 2002
"... 1 I n t roduct ion This extended abstract summarizes a new result for the graph compression problem, addressing how to compress a graph G into a binary string Z with the requirement that Z can be decoded to recover G. Graph compression finds important applications in 3D model compression of Computer ..."
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Cited by 16 (1 self)
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1 I n t roduct ion This extended abstract summarizes a new result for the graph compression problem, addressing how to compress a graph G into a binary string Z with the requirement that Z can be decoded to recover G. Graph compression finds important applications in 3D model compression of Computer Graphics [12, 1720] and compact routing table of Computer Networks [7}. For brevity, let a ~rgraph stand for a graph with property n. The informationtheoretically optimal number of bits required to represent an nnode ngraph is [log 2 N~(n)], where N,~(n) is the number of distinct nnode *rgraphs. Although determining or approximating the close forms of N ~ (n) for nontrivial classes of n is challenging, we provide a lineartime methodology for graph compression schemes that are informationtheoretically optimal with respect to continuous uperadditive functions (abbreviated as optimal for the rest of the extended abstract). 1 Specifically, if 7r satisfies certain properties, then we can compress any nnode medge 1rgraph G into a binary string Z such that G and Z can be computed from each other in O(m + n) time, and that the bit count of Z is at most fl(n) + o(fl(n)) for any continuous uperadditive function fl(n) with log 2 N~(n) < fl(n) + o(fl(n)). Our methodology is applicable to general classes of graphs; this extended abstract focuses on graphs with sublinear genus. 2 For example, if the input nnode,rgraph G is equipped with an embedding on its genus surface, which is a reasonable assumption for graphs arising from 3D model compression, then our methodology is applicable to any 7r satisfying the following statements:
Assembling 2D Blocks into 3D Chips
"... Threedimensional ICs promise to significantly extend the scale of system integration and facilitate newgeneration electronics. However, progress in commercial 3D ICs has been slow. In addition to technologyrelated difficulties, industry experts cite the lack of a commercial 3D EDA toolchain and ..."
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Threedimensional ICs promise to significantly extend the scale of system integration and facilitate newgeneration electronics. However, progress in commercial 3D ICs has been slow. In addition to technologyrelated difficulties, industry experts cite the lack of a commercial 3D EDA toolchain and design standards, high risk associated with a new technology, and high cost of transition from 2D to 3D ICs. To streamline the transition, we explore design styles that reuse existing 2D Intellectual Property (IP) blocks. Currently, these design styles severely limit the placement of ThroughSilicon Vias (TSVs) and constrain the reuse of existing 2D IP blocks in 3D ICs. To overcome this problem, we develop a methodology for using TSV islands and novel techniques for clustering nets to connect 2D IP blocks through TSV islands. Our empirical validation demonstrates 3D integration of traditional 2D circuit blocks without modifying their layout for this context.
Almost Square Packing
"... Abstract. The almost square rectangle packing problem involves packing all rectangles with sizes 1 × 2 to n × (n + 1) (almost squares) into an enclosing rectangle with minimal area. This extends the previously studied square packing problem by adding an additional degree of freedom for each rectangl ..."
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Abstract. The almost square rectangle packing problem involves packing all rectangles with sizes 1 × 2 to n × (n + 1) (almost squares) into an enclosing rectangle with minimal area. This extends the previously studied square packing problem by adding an additional degree of freedom for each rectangle, deciding in which orientation the item should be packed. We show how to extend the model and search strategy that worked well for square packing to solve the new problem. Some adapted versions of known redundant constraints improve overall search times. Based on a visualization of the search tree, we derive a decomposition method which initially only looks at the subproblem given by one of the cumulative constraints. This decomposition leads to further modest improvements of execution times. We find a solution for problem size 26 for the first time and dramatically improve best known times for finding solutions for smaller problem sizes by up to three orders of magnitude. 1
A LinearTime OptimalLength Encoding of Floorplans with ConstantTime Queries HaoYu Hung ∗ HsuehI Lu†
, 2011
"... A floorplan, which is also known as rectangular drawing, is a division of a rectangle into rectangular faces using horizontal and vertical line segments. Yamanaka and Nakano showed how to encode an nnode floorplan G in 2.5n bits. Chuang reduced the number of bits to at most 2.293n. Takahashi, Fujim ..."
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A floorplan, which is also known as rectangular drawing, is a division of a rectangle into rectangular faces using horizontal and vertical line segments. Yamanaka and Nakano showed how to encode an nnode floorplan G in 2.5n bits. Chuang reduced the number of bits to at most 2.293n. Takahashi, Fujimaki, and Inoue further reduced the number of bits to 2n. In this paper, we give an optimal solution to the problem of encoding G. Specifically, the firstorder term of the length of our encoding is informationtheoretically optimal, implying that our encoding has at most 1.878n + o(n) bits. Just like the previous results, our encoding and decoding algorithms run in O(n) time. Moreover, our encoding supports adjacency, degree, and neighborlisting queries in O(1) time per output. 1
mail.tsinghua.edu.cn †Advanced Technology Group
"... Abstract—Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized during 3D floorplanning, significantly increasing optimization complexity. Most existing floorplanners use combinatorial st ..."
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Abstract—Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized during 3D floorplanning, significantly increasing optimization complexity. Most existing floorplanners use combinatorial stochastic optimization techniques, hampering performance and scalability when used for 3D floorplanning. In this work, we propose and evaluate a scalable, temperatureaware, forcedirected floorplanner called 3DSTAF. Forcedirected techniques, although efficient at reacting to physical information such as temperature gradients, must eventually eliminate overlap. This can cause significant displacement when used for heterogeneous blocks. To smooth the transition from an unconstrained 3D placement to a legalized, layerassigned floorplan, we propose a threestage forcedirected optimization flow combined with new legalization techniques that eliminate white spaces and block overlapping during multilayer floorplanning. A temperaturedependent
mail.tsinghua.edu.cn
"... Abstract — Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized during 3D floorplanning, significantly increasing optimization complexity. Most existing floorplanners use combinatorial st ..."
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Abstract — Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized during 3D floorplanning, significantly increasing optimization complexity. Most existing floorplanners use combinatorial stochastic optimization techniques, hampering performance and scalability when used for 3D floorplanning. In this work, we propose and evaluate a scalable, temperatureaware, forcedirected floorplanner called 3DSTAF. Forcedirected techniques, although efficient at reacting to physical information such as temperature gradients, must eventually eliminate overlap. This can cause significant displacement when used for heterogeneous blocks. To smooth the transition from an unconstrained 3D placement to a legalized, layerassigned floorplan, we propose a threestage forcedirected optimization flow combined with new legalization techniques that eliminate white spaces and block overlapping during multilayer floorplanning. A temperaturedependent