Abstract. Testing is the process of stimulating a system with inputs in order to reveal hidden parts of the system state. In the case of non-deterministic systems, the difficulty arises that an input pattern can generate several possible outcomes. Some of these outcomes allow to distinguish between different hypotheses about the system state, while others do not. In this paper, we present a novel approach to find, for non-deterministic systems modeled as constraints over variables, tests that allow to distin-guish among the hypotheses as good as possible. The idea is to assess the quality of a test by determining the ratio of distinguishing (good) and not distinguishing (bad) outcomes. This measure refines previous notions proposed in the literature on model-based testing and can be computed using model counting techniques. We propose and analyze a greedy-type algorithm to solve this test optimization problem, using existing model counters as a building block. We give preliminary experimental results of our method, and discuss possible improvements. 1

bution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern genera-tion (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG proto-type used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Ex-perimental result showed that more reduced/compact test set can be generated from the high-level ATPG.

We study here schedulers for a class of rules that naturally arise in the context of rule-based constraint programming. We systematically derive a scheduler for them from a generic iteration algorithm of (Apt 2000). We apply this study to so-called membership rules of (Apt and Monfroy 2001). This leads to an implementation that yields a considerably better performance for these rules than their execution as standard CHR rules. Finally, we show how redundant rules can be identified and how appropriately reduced sets of rules can be computed.