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A proofproducing hardware compiler for a subset of higher order logic
 Oxford University
, 2005
"... (authors listed in alphabetical order) Abstract. Higher order logic (HOL) is a modelling language suitable for specifying behaviour at many levels of abstraction. We describe a compiler from a ‘synthesisable subset ’ of HOL function definitions to correctbyconstruction clocked synchronous hardware. ..."
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(authors listed in alphabetical order) Abstract. Higher order logic (HOL) is a modelling language suitable for specifying behaviour at many levels of abstraction. We describe a compiler from a ‘synthesisable subset ’ of HOL function definitions to correctbyconstruction clocked synchronous hardware. The compiler works by theorem proving in the HOL4 system and goes through several phases, each deductively refining the specification to a more concrete form, until a representation that corresponds to hardware is deduced. It also produces a proof that the generated hardware implements the HOL functions constituting the specification. Synthesised designs can be translated to Verilog HDL, simulated and then input to standard design automation tools. Users can modify the theorem proving scripts that perform compilation. A simple example is adding rewrites for peephole optimisation, but all the theoremproving infrastructure in HOL4 is available for tuning the compilation. Users can also extend the synthesisable subset. For example, the core system can only compile tailrecursions, but a ‘thirdparty ’ tool linRec is being developed to automatically generate tail recursive definitions to implement linear recursions, thereby extending the synthesisable subset of HOL to include linear recursion. 1
SatisfiabilityBased Program REASONING AND PROGRAM SYNTHESIS
, 2010
"... Program reasoning consists of the tasks of automatically and statically verifying correctness and inferring properties of programs. Program synthesis is the task of automatically generating programs. Both program reasoning and synthesis are theoretically undecidable, but the results in this disserta ..."
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Program reasoning consists of the tasks of automatically and statically verifying correctness and inferring properties of programs. Program synthesis is the task of automatically generating programs. Both program reasoning and synthesis are theoretically undecidable, but the results in this dissertation show that they are practically tractable. We show that there is enough structure in programs written by human developers to make program reasoning feasible, and additionally we can leverage program reasoning technology for automatic program synthesis. This dissertation describes expressive and efficient techniques for program reasoning and program synthesis. Our techniques work by encoding the underlying inference tasks as solutions to satisfiability instances. A core ingredient in the reduction of these problems to finite satisfiability instances is the assumption of templates. Templates are userprovided hints about the structural form of the desired artifact, e.g., invariant, pre and postcondition templates for reasoning; or program templates for synthesis. We propose novel algorithms, parameterized by suitable templates, that reduce the inference of these artifacts to satisfiability. We show that fixedpoint computation—the key technical challenge in program reasoning— is encodable as SAT instances. We also show that program synthesis can be viewed as generalized
The Reduceron reconfigured and reevaluated
"... A new version of a specialpurpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional ..."
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A new version of a specialpurpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in runtime performance. 1
A Framework for Refining Functional Specifications into Parallel Reconfigurable Hardware Implementations
, 2005
"... Reconfigurable logic devices such as the FPGA have brought about a revolution in the field of hardware design. The reduction in development costs has had a huge impact on broadening the scope of applications for which a hardware implementation is a realistic possibility. Current FPGA devices run to ..."
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Reconfigurable logic devices such as the FPGA have brought about a revolution in the field of hardware design. The reduction in development costs has had a huge impact on broadening the scope of applications for which a hardware implementation is a realistic possibility. Current FPGA devices run to many millions of gates, giving a huge potential for efficiency gains, benefiting from the inherently parallel nature of hardware circuits. These devices continue to grow in size, to the end that we can now seriously consider implementing even large scale systems purely in reconfigurable logic. Despite these advances, we find ourselves somewhat lacking in the tools and methodologies required to fully exploit this potential. Issues of hardware implementation and parallelism introduce significant complexity into the design process. We argue that without the correct approach, not only will this potential be under used, but the inherent complexity will undermine people’s
AVoCS 2005 Preliminary Version Automatic Formal Synthesis of Hardware from Higher Order Logic
"... Abstract A compiler is described that translates recursive function definitions in higher order logic to clocked synchronous hardware. Circuits are synthesised by formal proof mechanised in the HOL4 system. The logic terms representing hardware can be directly translated to Verilog HDL, simulated an ..."
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Abstract A compiler is described that translates recursive function definitions in higher order logic to clocked synchronous hardware. Circuits are synthesised by formal proof mechanised in the HOL4 system. The logic terms representing hardware can be directly translated to Verilog HDL, simulated and then input to standard design automation tools. The theorem proving scripts that perform compilation are extensible. A simple example is adding rewrites for peephole optimisation, but all the theoremproving infrastructure in HOL4 is available for tuning the compilation. The synthesisable subset can also be extended. For example, the core system can only compile tailrecursive function definitions, but a separate tool linRec is being developed to transform linear recursions to tail recursions, thereby extending the synthesisable subset to include linear recursion. 1 Introduction Our goal is to create correctbyconstruction hardware directly from mathematical specifications. The `synthesisable subset ' of logic is not intended to be fixed, but to grow as we do case studies. Currently, the compiler can automatically generate hardware to implement tail recursive function definitions. A typical example is the following iterative multiplyandaccumulate function: MultIter(m,n,acc) =
Technical Report Number 682 Translating HOL
, 2007
"... Translating HOL functions to hardware ..."
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