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PWave: A Multisource Multisink Anycast Routing Framework for Wireless Sensor Networks
"... Abstract. We propose a novel routing framework called PWave that supports multisource multisink anycast routing for wireless sensor networks. A distributed and scalable potential field estimation algorithm and a probabilistic forwarding scheme are proposed to ensure low overhead and high resilienc ..."
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Abstract. We propose a novel routing framework called PWave that supports multisource multisink anycast routing for wireless sensor networks. A distributed and scalable potential field estimation algorithm and a probabilistic forwarding scheme are proposed to ensure low overhead and high resilience to network dynamics. Key properties of this framework are proved through theoretical analysis and verified through simulations.Using network lifetime maximization problem as one example, we illustrated the power of this framework by showing a 2.7 to 8 times lifetime extension over Directed Diffusion and up to 5 times lifetime extension over the energyaware multipath routing. 1
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations
"... Abstract — This paper solves the variationaware onchip decoupling capacitance (decap) budgeting problem. Unlike previous work assuming the worstcase current load, we develop a novel stochastic current model, which efficiently and accurately captures operation variation such as temporal correlatio ..."
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Abstract — This paper solves the variationaware onchip decoupling capacitance (decap) budgeting problem. Unlike previous work assuming the worstcase current load, we develop a novel stochastic current model, which efficiently and accurately captures operation variation such as temporal correlation between clock cycles and logicinduced correlation between ports. The models also considers current variation due to process variation with spatial correlation. We then propose an iterative alternative programming algorithm to solve the decap budgeting problem under the stochastic current model. Experiments using industrial examples show that compared with the baseline model which assumes maximum currents at all ports and under the same decap area constraint, the model considering temporal correlation reduces the noise by up to 5×, and the model considering both temporal and logicinduced correlations reduces the noise by up to 17×. Compared with the model using deterministic process parameters, considering process variation (Leff variation in this paper) reduces the mean noise by up to 4× and the 3σ noise by up to 13×. While the existing stochastic optimization has been used mainly for process variation purpose, this paper to the best of our knowledge is the first indepth study on stochastic optimization taking into account both operation and process variations for power network design. We convincingly show that considering operation variation is highly beneficial for power integrity optimization and this should be researched for optimizing signal and thermal integrity as well. I.
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching
 in Proc. ISQED, 2006
"... This paper proposes a novel method for analyzing large onchip power delivery networks via a stochastic moment matching (SMM) method. The proposed method extends the existing direct stochastic random walk method that can be only applied to DC analysis in purely resistive networks or transient analysi ..."
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This paper proposes a novel method for analyzing large onchip power delivery networks via a stochastic moment matching (SMM) method. The proposed method extends the existing direct stochastic random walk method that can be only applied to DC analysis in purely resistive networks or transient analysis of RC networks with low efficiency. The new method can analyze general structure RLC networks by combining the stochastic process with frequency domain moment matching technique. As a result, we achieve better scalability than traditional frequency domain P/G analysis approaches, and better efficiency than existing random walk transient analysis techniques. Our experimental results show that SMM can easily trade efficiency for accuracy or vise versa. SMM can easily deliver 10X100X speedup over a LUbased direct solver and about 10X speedup over the pure random walk method with reasonable accuracy on large industry P/G networks. 1
A realistic earlystage power grid verification algorithm based on hierarchical constraints
 IEEE Trans. ComputerAided Design
, 2012
"... Abstract—Power grid verification has become an indispensable step to guarantee a functional and robust chip design. Vectorless power grid verification methods, by solving linear programming (LP) problems under current constraints, enable worstcase voltage drop predictions at an early stage of desig ..."
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Abstract—Power grid verification has become an indispensable step to guarantee a functional and robust chip design. Vectorless power grid verification methods, by solving linear programming (LP) problems under current constraints, enable worstcase voltage drop predictions at an early stage of design when the specific waveforms of current drains are unknown. In this paper, a novel power grid verification algorithm based on hierarchical constraints is proposed. By introducing novel power constraints, the proposed algorithm generates more realistic current patterns and provides less pessimistic voltage drop predictions. The model order reductionbased coefficient computation algorithm reduces the complexity of formulating the LP problems from being proportional to steps to being independent of steps. Utilizing the special hierarchical constraint structure, the submodular polyhedron greedy algorithm dramatically reduces the complexity of solving the LP problems from over O(k3m) to roughly O(km log km), where km is the number of variables. Numerical results have shown that the proposed algorithm provides less pessimistic voltage drop prediction while at the same time achieves dramatic speedup. Index Terms—Hierarchical constraints, model order reduction, submodular polyhedron, vectorless power grid verification, worstcase voltage drop. I.
A Hierarchical Matrix Inversion Algorithm for Vectorless Power Grid Verification
"... Abstract—Vectorless power grid verification is a powerful technique to validate the robustness of the onchip power distribution network for all possible current waveforms. Formulated and solved as linear programming problems, vectorless power grid verification demands intensive computational power ..."
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Abstract—Vectorless power grid verification is a powerful technique to validate the robustness of the onchip power distribution network for all possible current waveforms. Formulated and solved as linear programming problems, vectorless power grid verification demands intensive computational power due to the large number of nodes in modern power grids. Previous work showed that the performance bottleneck of this powerful technique is within the subproblem of power grid analysis, which essentially computes the inverse of the sparse but large power grid matrix. In this paper, we propose a hierarchical matrix inversion algorithm to compute the rows of the inverse efficiently by exploiting the structure of the power grid. The proposed algorithm is integrated with a previous dual algorithm addressing an orthogonal subproblem for vectorless power grid verification. Results show that the proposed hierarchical algorithm accelerates the matrix inversion significantly, and thus makes the overall vectorless power grid verification efficient. I.
Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence
"... Abstract—As technology advances, the metal width decreases while the global wire length increases. This trend makes the resistance of the power wire increase substantially. Furthermore, the threshold voltage scales nonlinearly, raising the ratio of the threshold voltage to the supply voltage and mak ..."
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Abstract—As technology advances, the metal width decreases while the global wire length increases. This trend makes the resistance of the power wire increase substantially. Furthermore, the threshold voltage scales nonlinearly, raising the ratio of the threshold voltage to the supply voltage and making the voltage (IR) drop in the power/ground (P/G) network a serious problem in modern IC design. Traditional P/G networkanalysis methods are often very computationally expensive, and it is, thus, not feasible to cosynthesize P/G network with floorplan. To make the cosynthesis feasible, we need not only an efficient, effective, and flexible floorplanning algorithm but also a very efficient yet sufficiently accurate P/G networkanalysis method. In this paper, we present a method for floorplan and P/G network cosynthesis based on an efficient P/G networkanalysis scheme and the B∗tree floorplan representation. We integrate the cosynthesis into a commercial design flow to develop an effective powerintegrity (IR drop)driven design methodology. Experimental results based on a realworld circuit design and the MCNC benchmarks show that our design methodology successfully fixes the IRdrop errors earlier at the floorplanning stage and, thus, enables the singlepass design convergence. Index Terms—Electromigration, floorplanning, IR drop, physical design, power/ground (P/G) analysis, power integrity, simulated
SoC test architecture design and optimization considering power supply noise effects
 In Proceedings IEEE International Test Conference (ITC), paper 26.2
, 2008
"... Excessive power supply noise (PSN) during testing can erroneously cause good chips to fail the manufacturing test, thus leading to unnecessary yield loss. While there are some emerging methodologies such as PSNaware test generation technique to tackle this problem, they are not readily applicable i ..."
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Excessive power supply noise (PSN) during testing can erroneously cause good chips to fail the manufacturing test, thus leading to unnecessary yield loss. While there are some emerging methodologies such as PSNaware test generation technique to tackle this problem, they are not readily applicable in modular systemonachip (SoC) testing. This is because: (i). embedded core tests are usually prepared by core providers who are not knowledgeable about the SoC power distribution network; (ii) embedded cores are usually tested in parallel to reduce testing time, but the associated intercore PSN effects are not considered in existing SoC test architecture design and optimization process. In this paper, we present a fast intercore PSN estimation method and use it to guide the test scheduling process to solve the PSNinduced SoC test yield loss problem. In addition, upon observing that the PSN effects usually manifest themselves only during the capture phase for scantested cores, we introduce novel design for test (DfT) structures into SoC test controller to avoid PSN effects with negligible testing time penalty. Experimental results demonstrate the effectiveness of the proposed solution. 1
Overcoming Variations in NanometerScale Technologies
"... Abstract — Nanometerscale circuits are fundamentally different from those built in their predecessor technologies in that they are subject to a wide range of new effects that induce onchip variations. These include effects associated with printing finer geometry features, increased atomicscale ef ..."
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Abstract — Nanometerscale circuits are fundamentally different from those built in their predecessor technologies in that they are subject to a wide range of new effects that induce onchip variations. These include effects associated with printing finer geometry features, increased atomicscale effects, and increased onchip power densities, and are manifested as variations in process and enviromental parameters and as circuit aging effects. The impact of such variations on key circuit performance metrics is quite significant, resulting in parametric variations in the timing and power, and potentially catastrophic failure due to reliability and aging effects. Such problems have led to a revolution in the way that chips are designed in the presence of such uncertainties, both in terms of performance analysis and optimization. This paper presents an overview of the root causes of these variations and approaches for overcoming their effects. I.