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Buildmaster: Efficient asip architecture exploration through compilation and simulation result caching
- in DDECS 2014
, 2014
"... Abstract—In this paper we introduce and discuss the Build-Master framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can ..."
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Abstract—In this paper we introduce and discuss the Build-Master framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluation of selected designs. In each of the experiments we performed, we were able to reduce the number of required simulations with over 90 % and save up to 50 % on the required compilation time. I.
An Integrated ASIP Design Flow for Digital Signal Processing Applications (Invited Paper)
"... Abstract—Application specific instruction set processors (ASIP) allow designers to optimize the architecture of an embedded processor to meet the specific demands of a particular application. A complementary form of customization is provided by domain-specific models of computation (MoCs), which can ..."
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Abstract—Application specific instruction set processors (ASIP) allow designers to optimize the architecture of an embedded processor to meet the specific demands of a particular application. A complementary form of customization is provided by domain-specific models of computation (MoCs), which can expose the high level structure of applications that is useful for various kinds of optimizing design transformations. One such MoC is Synchronous Dataflow (SDF), which is used increasingly in the design and implementation of signal processing applications. In this paper, we develop an integration of SDF- and ASIP-oriented design flows, and use this integrated design flow to explore trade-offs in the space of hardware/software implementations. We also explore an approach to ASIP implementation in terms of “critical ” and “non-critical ” applications, which allows designers to tune the degree of specialization for a targeted ASIP. Our results show that single ASIP processor tuned for pair of critical applications saves 26 % to 50 % of area required for implementations of two applications on separate ASIPs and noncritical applications runs on such processor with in worst case 4.5 % overhead for our selection of benchmarks. I.
*Department of Computer Systems
"... Abstract-Data-flow based design environments bring advantages of specification, validation and synthesis to embedded systems design by decoupling computation from transfer of data. The former is performed by actors, and data transfer between actors and an execution order of actors is determined by s ..."
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Abstract-Data-flow based design environments bring advantages of specification, validation and synthesis to embedded systems design by decoupling computation from transfer of data. The former is performed by actors, and data transfer between actors and an execution order of actors is determined by scheduling and buffering strategies. In this work, we examine code sizes and cycle counts resulting from combinations of scheduling and buffering techniques. The experiments were carried out by designing an application specific instructionset processor streamlined for each of the benchmarks, using a codesign environment called TeE. We also show what additional overhead is introduced when an architecture implemented using our approach is employed for an application outside its targeted domain. I.
