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**1 - 4**of**4**### LOW COEFFICIENT COMPLEXITY APPROXIMATIONS OF THE ONE DIMENSIONAL DISCRETE COSINE TRANSFORM

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### EURASIP Journal on Applied Signal Processing 2003:6, 543–554 c ○ 2003 Hindawi Publishing Corporation Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations

, 2002

"... A method for the rapid design of field programmable gate array (FPGA)-based discrete cosine transform (DCT) approximations is presented that can be used to control the coding gain, mean square error (MSE), quantization noise, hardware cost, and power consumption by optimizing the coefficient values ..."

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A method for the rapid design of field programmable gate array (FPGA)-based discrete cosine transform (DCT) approximations is presented that can be used to control the coding gain, mean square error (MSE), quantization noise, hardware cost, and power consumption by optimizing the coefficient values and datapath wordlengths. Previous DCT design methods can only control the quality of the DCT approximation and estimates of the hardware cost by optimizing the coefficient values. It is shown that it is possible to rapidly prototype FPGA-based DCT approximations with near optimal coding gains that satisfy the MSE, hardware cost, quantization noise, and power consumption specifications.

### EURASIP Journal on Applied Signal Processing 2003:6, 555–564 c ○ 2003 Hindawi Publishing Corporation A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs

, 2002

"... Area-efficient peak-constrained least-squares (PCLS) bit-serial finite impulse response (FIR) filter implementations can be rapidly prototyped in field programmable gate arrays (FPGA) with the methodology presented in this paper. Faster generation of the FPGA configuration bitstream is possible with ..."

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Area-efficient peak-constrained least-squares (PCLS) bit-serial finite impulse response (FIR) filter implementations can be rapidly prototyped in field programmable gate arrays (FPGA) with the methodology presented in this paper. Faster generation of the FPGA configuration bitstream is possible with a new application-specific mapping and placement method that uses JBits to avoid conventional general-purpose mapping and placement tools. JBits is a set of Java classes that provide an interface into the Xilinx Virtex FPGA configuration bitstream, allowing the user to generate new configuration bitstreams. PCLS coefficient generation allows passband-to-stopband energy ratio (PSR) performance to be traded for a reduction in the filter’s hardware cost without altering the minimum stopband attenuation. Fixed-point coefficients that meet the frequency response and hardware cost specifications can be generated with the PCLS method. It is not possible to meet these specifications solely by the quantization of floating-point coefficients generated in other methods.

### LOW COEFFICIENT COMPLEXITY APPROXIMATIONS OF THE ONE DIMENSIONAL DISCRETE COSINE TRANSFORM

"... A method for the design of arbitrarily exact Discrete Cosine Transform (DCT) approximations that permit perfect recon-struction using fixed point arithmetic is presented. Sim-ple quantization of floating point precision coefficients typ-ically leads to DCT approximations which fail to meet the codin ..."

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A method for the design of arbitrarily exact Discrete Cosine Transform (DCT) approximations that permit perfect recon-struction using fixed point arithmetic is presented. Sim-ple quantization of floating point precision coefficients typ-ically leads to DCT approximations which fail to meet the coding gain, Mean Square Error (MSE), and coefficient com-plexity (number of coefficient adders and subtractors) spec-ifications. It is shown that it is possible to design DCT ap-proximations with near optimal coding gains that meet the MSE and coefficient complexity requirements. Finite preci-sion effects are discussed for these DCT approximations. 2.