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et al. Data distribution support on distributed shared memory multiprocessors
- ACM SIGPLAN Notices
, 1997
"... Abstract — On multi-core processors, memories are preferably ..."
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Abstract — On multi-core processors, memories are preferably
Run-time partitioning of hybrid distributed shared memory on multi-core network-onchips
- In The 3rd IEEE International Symposium on Parallel Architectures, Algorithms and Programming (PAAP 2010
, 2010
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Fault resilient real-time design for noc architectures
- In CyberPhysical Systems (ICCPS), 2012 IEEE/ACM Third International Conference on
, 2012
"... Abstract—Performance and time to market requirements cause many real-time designers to consider components, off the shelf (COTS) for real-time cyber-physical systems. Massive multi-core embedded processors with network-on-chip (NoC) designs to facilitate core-to-core communication are becoming commo ..."
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Abstract—Performance and time to market requirements cause many real-time designers to consider components, off the shelf (COTS) for real-time cyber-physical systems. Massive multi-core embedded processors with network-on-chip (NoC) designs to facilitate core-to-core communication are becoming common in COTS. These architectures benefit real-time scheduling, but they also pose predictability challenges. In this work, we develop a framework for Fault Observant and Correcting Real-Time Embedded design (Forte) that utilizes massive multi-core NoC designs to reduce overhead by up to an order of magnitude and to lower jitter in systems via utilizing message passing instead of shared memory as the means for intra-processor communication. Message passing, which is shown to improve the overall scalability of the system, is utilized as the basis for replication and task rejuvenation. This improves fault resilience by orders of magnitude. To our knowledge, this work is the first to systematically map real-time tasks onto massive multi-core processors with support for fault tolerance that considers NoC effects on scalability on an real hardware platform and not just in simulation. I.
Multiprocessor system-on-chip (MP-SoC) architectures
, 2007
"... www.elsevier.com/locate/sysarc Exploration of distributed shared memory architectures for NoC-based multiprocessors ..."
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www.elsevier.com/locate/sysarc Exploration of distributed shared memory architectures for NoC-based multiprocessors
in Distributed Shared Memory based multi-core Network-on-Chips
"... journal homepage: www.elsevier.com/locate/compeleceng Reducing Virtual-to-Physical address translation overhead ..."
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journal homepage: www.elsevier.com/locate/compeleceng Reducing Virtual-to-Physical address translation overhead
ABSTRACT ZIMMER, CHRISTOPHER J. Bringing Efficiency and Predictability to Massive Multi-core
"... Massive multi-core network-on-chip (NoC) processors represent the next stage in both embedded and general purpose computing. These novel architecture designs with abundant processing resources and increased scalability address the frequency limits of modern processors, power/leakage constraints, and ..."
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Massive multi-core network-on-chip (NoC) processors represent the next stage in both embedded and general purpose computing. These novel architecture designs with abundant processing resources and increased scalability address the frequency limits of modern processors, power/leakage constraints, and the scalability limits of system bus interconnects. NoC architectures are particularly interesting in both the real-time embedded and high-performance computing domains. Abundant processing resources have the potential to simplify scheduling and represent a shift away from single core utilization concerns e.g., within the model of the “dark silicon ” abstraction that promotes a 1-to-1 task-to-core mapping with frequent core activations/deactivations. Additionally, due to silicon constraints, massive multi-core processors often contain simplified processor pipelines that provide an increase in predictability analysis beneficial for real-time systems. Also, simplified processor pipelines coupled with high-performance interconnects often result in low power utilization that is beneficial in high-performance systems. While suitable in many ways, these architectures are not without their own challenges. Reliance on shared memory and the strain that massive multi-core processors can put on memory controllers represent a significant challenge to predictability and performance. Resilience is
A Fault Observant Real-Time Embedded Design for Network-on-Chip Control Systems ∗
"... Performance and time to market requirements cause many realtime designers to consider components, off the shelf (COTS) for real-time systems. Massive multi-core embedded processors with network-on-chip (NoC) designs to facilitate core-to-core communication are becoming common in COTS. These architec ..."
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Performance and time to market requirements cause many realtime designers to consider components, off the shelf (COTS) for real-time systems. Massive multi-core embedded processors with network-on-chip (NoC) designs to facilitate core-to-core communication are becoming common in COTS. These architectures benefit real-time scheduling, but they also pose predictability challenges. In this work, we develop a framework for Fault Observant Real-Time Embedded design (Forte) that utilizes massive multi-core NoC designs to reduce overhead by up to an order of magnitude and to lower jitter in systems via utilizing message passing instead of shared memory as the means for intra-processor communication. Message passing, which is shown to improve the overall scalability of the system, is utilized as the basis for replication and task rejuvenation to improve fault resilience by orders of magnitude. To our knowledge, this work is the first to systematically map real-time tasks onto massive multi-core processors with support for fault tolerance that considers NoC effects on scalability on an actual massive multi-core hardware platform. 1.
47Journal Integrated Circuits and Systems 2012; v.7 / n.1:47-60 Distributed Shared Memory for NoC-based MPSoCs
"... The architecture of anMPSoCmay be composed of elements such as: PEs, memory elements and a communi-cation infrastructure.According to [1], one of the most crit-ical components that determine the success of an MPSoC ..."
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The architecture of anMPSoCmay be composed of elements such as: PEs, memory elements and a communi-cation infrastructure.According to [1], one of the most crit-ical components that determine the success of an MPSoC
A Novel NoC–Based Design for Fault-Tolerance of Last-Level Caches in CMPs
"... Advances in technology scaling, coupled with aggressive voltage scaling results in significant reliability challenges for emerging Chip Multiprocessor (CMP) platforms, where error-prone caches continue to dominate the chip area. Network-on-Chip (NoC) fabrics are increasingly used to manage the scala ..."
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Advances in technology scaling, coupled with aggressive voltage scaling results in significant reliability challenges for emerging Chip Multiprocessor (CMP) platforms, where error-prone caches continue to dominate the chip area. Network-on-Chip (NoC) fabrics are increasingly used to manage the scalability of these CMPs. We present a novel fault-tolerant scheme for Last Level Cache (LLC) in CMP architectures that leverages the interconnection network to protect the LLC cache banks against permanent faults. During a LLC access to a faulty area, the network detects and corrects the faults, returning the fault-free data to the requesting core. By leveraging the NoC interconnection fabric, we can implement any cache fault-tolerant scheme in an efficient, modular, and scalable manner. We perform extensive design space exploration on NoC benchmarks to demonstrate the utility and efficacy of our approach. The overheads of leveraging the NoC fabric are minimal: on an 8-core, 16-cache-bank CMP we demonstrate reliable access to LLCs with additional overheads of less than 3 % in area and less than 7 % in power.
DISTRIBUTED MEMORY ORGANIZATION WITH SUPPORT FOR DATA MIGRATION FOR
, 2011
"... alguns colegas que abandonam a batalha. Mas guerreiro que é guerreiro persiste, confia em deus, e acaba a sua jornada com sucesso. A minha jornada foi de grande aprendizado, alegrias, tristezas, cansaços, esforços, mas no fim, valeu muito a pena. Eu faria novamente. Desta forma, gostaria de agradece ..."
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alguns colegas que abandonam a batalha. Mas guerreiro que é guerreiro persiste, confia em deus, e acaba a sua jornada com sucesso. A minha jornada foi de grande aprendizado, alegrias, tristezas, cansaços, esforços, mas no fim, valeu muito a pena. Eu faria novamente. Desta forma, gostaria de agradecer a todos que me ajudaram e apoiaram durante estes dois anos (2010-2012). A meus pais, Carlos e Joseane, muito obrigado pelo incentivo, apoio e educação que me deram. A minha companheira, Bruna, obrigado pela enorme paciência, amor e compreensão que teve e ainda tem comigo. Gostaria também de agradecer a meus avós paternos, Ocir e Rodi, que sempre me apoiam, em qualquer momento da minha vida. Também aos meus
