Results 1 -
2 of
2
Leakage Power Reduction for Deeply-Scaled FinFET Circuits Operating in Multiple Voltage Regimes Using Fine-Grained Gate- Length Biasing Technique
"... Abstract-With the aggressive downscaling of the process technologies and importance of battery-powered systems, reducing leakage power consumption has become one of the most crucial design challenges for IC designers. This paper presents a devicecircuit cross-layer framework to utilize fine-grained ..."
Abstract
- Add to MetaCart
(Show Context)
Abstract-With the aggressive downscaling of the process technologies and importance of battery-powered systems, reducing leakage power consumption has become one of the most crucial design challenges for IC designers. This paper presents a devicecircuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in the near-and super-threshold operation regimes. The impacts of Gate-Length Biasing (GLB) on circuit speed and leakage power are first studied using one of the most advanced technology nodes -a 7nm FinFET technology. Then multiple standard cell libraries using different leakage reduction techniques, such as GLB and Dual-VT, are built in multiple operating regimes at this technology node. It is demonstrated that, compared to Dual-VT, GLB is a more suitable technique for the advanced 7nm FinFET technology due to its capability of delivering a finer-grained trade-off between the leakage power and circuit speed, not to mention the lower manufacturing cost. The circuit synthesis results of a variety of ISCAS benchmark circuits using the presented GLB 7nm FinFET cell libraries show up to 70% leakage improvement with zero degradation in circuit speed in the near-and super-threshold regimes, respectively, compared to the standard 7nm FinFET cell library.
unknown title
"... Abstract — FinFET devices have been proposed as a promising substitute for the conventional bulk CMOS-based devices at the nanoscale, due to their extraordinary properties such as improved channel controllability, high ON/OFF current ratio, reduced short-channel effects, and relative immunity to gat ..."
Abstract
- Add to MetaCart
(Show Context)
Abstract — FinFET devices have been proposed as a promising substitute for the conventional bulk CMOS-based devices at the nanoscale, due to their extraordinary properties such as improved channel controllability, high ON/OFF current ratio, reduced short-channel effects, and relative immunity to gate line-edge roughness. This paper builds standard cell libraries for an advanced 7nm FinFET technology, supporting multiple threshold voltages and supply voltages. Circuit synthesis results of various combinational and sequential circuits based on presented 7nm FinFET standard cell libraries forecast 10X and 1000X energy reductions on average in the super-threshold regime, and 16X and 3000X energy reductions on average in the near-threshold regime, compared to those results of 14nm and 45nm bulk CMOS technology nodes, respectively. Index Terms — FinFET; 7nm technology; standard cell library;
