ter verkrijging van de graad van doctor aan de Technische Universiteit Eindhoven, op gezag van de rector magnificus prof.dr.ir. F.P.T. Baaijens, voor een commissie aangewezen door het College voor Promoties, in het openbaar te verdedigen op maandag

Abstract—In this paper, a motion estimation processor (MEP) with 3D stacked memory architecture is proposed to 1) reduce the memory and core power consumption; 2) provide higher bandwidth. Firstly, a memory die is designed and staked with MEP die. By adding face-to-face (F2F) pad and through silicon vias (TSV) definitions, 2D electronic design automation (EDA) tools are extended to support the proposed 3D stacking architec-ture. Moreover, a novel memory controller is applied to control the data transmission and the timing between memory die and MEP die. Finally, 3D physical design is completed for the whole system including TSV/F2F placement, floor plan optimization, power network generation, etc. Comparing with 2D technology, the number of IO pins is reduced by 77%. After optimizing the floor plan of the MEP die and memory die, the routing wire length is reduced by 13.4 % and 50 % respectively. The simulation results show that the max bandwidth is more than 14GB/s and whole design can support real-time