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...(also called SIMD register) utilization and regularizing the memory access pattern was deeply studied and methods such as register blocking [7], [25] or by using different matrix storage formats [4], =-=[13]-=- have been proposed. Yet the most efficient method to regularize the memory access pattern is to multiply a sparse matrix by multiple vectors. When the multiple vectors are organized as a dense matrix...

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...sThis sensitivity of performance to the average numbersof nonzero elements per row is shared, although possiblysto a lesser extent, by conventional SpMV and SpMM implementations (on CPU and GPU)s[19] =-=[42]-=-.sThe difference in execution times of the “AP” algorithm with respect to binary vs. floating point matrices issa result of the difference in Boolean vs. associative multiplication times.sFor smaller ...

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...removed to/from G, to maintain the identical vertex sets, we first subtract u and v from their sets and insert them to new ones. Candidates for being identical vertices are found using a hash function and the overall cost of maintaining the data structure is OðnþmÞ [27]. 2.5. Simultaneous source traversal The performance of sparse kernels is mostly hindered by irregular memory accesses. The most famous example for sparse computation is the multiplication of a sparse matrix by a dense vector (SpMV). Several techniques, like register blocking [6,33] and usage of different matrix storage formats [2,21], are proposed to regularize the memory access pattern. However, multiplying a sparse matrix by multiple vectors is the most efficient and popular technique to regularize the memory access pattern. Once the multiple vectors are organized as a dense matrix, the problem becomes the multiplication of a sparse matrix by a dense matrix (SpMM). Each nonzero of the sparse matrix causes the multiplication of a single element of the vector in SpMV, and it results in the multiplications of as many consecutive elements of the dense matrix as its number of columns in SpMM. Accommodating that idea for clos...

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...lumn indexing information and nonzero values. Taking the standard CSR format as a starting point, we derived a vectorized kernel for SpMV. 2.1 Vectorized Kernel For CSR, a natural way to parallelize the SpMV is to assign the subsets of rows to execution units.The elementary operation is then shrinked into the product of a compressed sparse vector with a dense vector. By using the SIMD instruction we insert at the lowest dimension a parallelism resulting from the vectorization. In this direction we propose the row-wise vectorized kernel for SpMV, which is similar to recent work on SpMV for MIC [3]. The Alg. 1 delineates the SIMDized kernel that handles the row-wise multiplication. The writemask functions as a window ensuring only the lower portion of vector being operated when there’re less than 8 nonzeros left in a row. The “8” in Alg. 1 implies 8 double precision floating numbers that occupy the 512-bits SIMD units in MIC. 2.2 Hierarchical Exploitation of Hardware Resources The second dimension of parallelism is built upon the number of cores. Along with the hierarchical memory subsystem, these computational resources can be exploited by the execution units spawned and managed by the...

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...ls and tools including OpenMP withsthe use of Xeon Phi intrinsics and worked on two key building blocks for FEASTFLOW, i.e. scalar-vectorsproduct (axpy) and sparse-matrix vector multiplication (spmv) =-=[2, 3, 4, 7]-=- . Our experimental results indicatedsthat the Intel MIC architecture can serve as a promising accelerator for our software infrastructure.sThe rest of this paper is organized as follows: In section 2...

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...mous example for sparse computation is the multiplication of a sparse matrix by a dense vector (SpMV). Several techniques, like register blocking [6, 33] and usage of different matrix storage formats =-=[2, 21]-=-, are proposed to regularize the memory access pattern. However, multiplying a sparse matrix by multiple vectors is the most efficient and popular technique to regularize the memory access pattern. On...

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...te, instead of being restarted. Some essays are focused in the implementation of existing algorithms into coprocessors. For example, [33] developed a multi-node 1D FFT implementation on coprocessors; =-=[27]-=- implemented a sparse matrix-vector multiplication; and [32] developed a SQL engine that benefited from the inherent parallelism related to Xeon Phi coprocessors. Furthermore, as it is the case, there...

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...is makes it suitable for a wider range of problems, including Sluga et al. BMC Bioinformatics 2014, 15:216 Page 5 of 8 http://www.biomedcentral.com/1471-2105/15/216 multiplications of sparse matrices =-=[19]-=-, and operations on trees and graphs [20]. Intel provides a C++ compiler suite and all the tools needed to exploit the hardware [21]. The code can be parallelized using OpenMP directives or the MPI li...

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... addition to these studies, parallel breadth-first search (BFS), which is the main building block to compute closeness centrality values, has been widely studied on shared-memory systems such as GPUs =-=[10, 15, 19]-=- and Intel Xeon Phi [27]. Since these work focus on the parallelization of a single BFS, their natural extension to CC will yield the iterative execution of a fine-grain parallel CC kernel responsible...

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...s, including spMVM, on this architecture. First work from Saule et al. [13] is based on the (vectorized) CRS format and showed that this format is in general not suited for Intel Xeon Phi. Liu et al. =-=[14]-=- have recently published a sparse matrix data format for the Intel Xeon Phi that is very similar to ours. They have obtained much better performance 2 than with CRS, but the performance analysis of th...