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... runtime in every read and write to shared memory. As a result, STMs impose some overhead in sequential executions, but they are efficient enough to pay off with some meaningful degree of parallelism =-=[11, 12]-=-. Recently, implementations in hardware (HTM) became available in commercial processors delivered by major industry players. Beyond Intel, IBM also provided support for HTM [16], in processors mostly ...

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... as an extension to multi-processors’ cache coherence protocols [27]. Due to the difficulty of rapid prototyping in hardware environments, researchers resorted to STMs to advance the state of the art =-=[18, 17, 16, 14]-=-. Simultaneously, hardware-based implementations have also been proposed, whose designs were validated using simulators [25]. The concern for both performance and power consumption metrics has been on...

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...n exploit the hardware parallelism of those processors. The current widely used concurrent collections of elements (e.g., Linked-List, Skip-List, Tree) are well optimized for high performance and ensure isolation of atomic operations, but they do not compose. This is a significant limitation from a programmability standpoint, especially for legacy systems as they are increasingly migrated onto multicore hardware (for high performance) and must seamlessly integrate with third-party libraries. Software transactional memory (STM) [20] can be used to implement transactional data structures (e.g., [7,12]), which makes them composable – a significant benefit. However, monitoring all of the memory locations accessed by a transaction while executing data structure operations is a significant (and often unnecessary) overhead. As a result, STM-based transactional collections perform inferior to their optimized, concurrent (i.e. non-transactional) counterparts. As an alternative to STM, the transactional boosting methodology was introduced in [14] and further investigated in [11], to convert the highly concurrent data structures into transactional ones. Briefly, in [14], semantic locks are pessimis...

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...s, e.g., to use logical clocks to obtain consistent snapshots at “close” physical times. 26 clocks, allow for providing stronger real-time guarantees? Would relaxing the progress guarantees for read-only transactions (e.g., lock-freedom in systems like Spanner or GMU) allow for strengthening the real-time ordering guarantees that a GPR system can guarantee? One may argue that the above questions appear related to some of the theoretical problems studied by the parallel/concurrent computing literature, which investigated the possibility of building scalable Transactional Memory implementations [23, 47, 14, 24] that guarantee a property akin to GPR, namely Disjoint Access Parallelism (DAP) [25, 5, 10, 39]: roughly speaking, in a DAP system two transactions that access disjoint data items cannot contend for any shared object (like logical clocks). However these works considered a different system model (shared-memory systems) and neglected the usage of physical and hybrid clocks. Understanding whether those results apply to the case of distributed data stores (i.e., message-passing model) using different clock types remains an interesting open research problem. 6.2 The Trade-offs Between Logical and ...