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Temperatureaware scheduling and assignment for hard realtime applications on MPSoCs
, 2010
"... Increasing integrated circuit (IC) power densities and temperatures may hamper multiprocessor systemonchip (MPSoC) use in hard realtime systems. This article formalizes the temperatureaware realtime MPSoC assignment and scheduling problem and presents an optimal phased steadystate mixed intege ..."
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Cited by 42 (1 self)
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Increasing integrated circuit (IC) power densities and temperatures may hamper multiprocessor systemonchip (MPSoC) use in hard realtime systems. This article formalizes the temperatureaware realtime MPSoC assignment and scheduling problem and presents an optimal phased steadystate mixed integer linear programming based solution that considers the impact of scheduling and assignment decisions on MPSoC thermal profiles to directly minimize the chip peak temperature. We also introduce a flexible heuristic framework for task assignment and scheduling that permits system designers to trade off accuracy for running time when solving large problem instances. Finally, for task sets with sufficient slack, we show that inserting idle times between task executions can further reduce the peak temperature of the MPSoC quite significantly.
Thermal Monitoring of Real Processors: Techniques for Sensor Allocation and Full Characterization. Order A Journal On The Theory Of Ordered Sets And Its Applications
, 2010
"... ABSTRACT The increased power densities of multicore processors and the variations within and across workloads lead to runtime thermal hot spots locations of which change across time and space. Thermal hot spots increase leakage, deteriorate timing, and reduce the mean time to failure. To manage ru ..."
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Cited by 10 (1 self)
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ABSTRACT The increased power densities of multicore processors and the variations within and across workloads lead to runtime thermal hot spots locations of which change across time and space. Thermal hot spots increase leakage, deteriorate timing, and reduce the mean time to failure. To manage runtime thermal variations, circuit designers embed withindie thermal sensors that acquire temperatures at few selected locations. The acquired temperatures are then used to guide runtime thermal management techniques. The capabilities of these techniques are essentially bounded by the spatial thermal resolution of the sensor measurements. In this paper we characterize temperature signals of real processors and demonstrate that onchip thermal gradients lead to sparse signals in the frequency domain. We exploit this observation to (1) devise thermal sensor allocation techniques, and (2) devise signal reconstruction techniques that fully characterize the thermal status of the processor using the limited number of measurements from the thermal sensors. To verify the accuracy of our methods, we compare our temperature characterization results against thermal measurements acquired from a stateoftheart infrared camera that captures the midband infrared emissions from the back of the die of a 45 nm dualcore processor. Our results show that our techniques are capable of accurately characterizing the temperatures of real processors.
S.: Performance Optimal Processor Throttling Under Thermal Constraints
 In: CASES ’07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
, 2007
"... We derive analytically, the performance optimal throttling curve for a processor under thermal constraints for a given task sequence. We found that keeping the chip temperature constant requires an exponential speed curve. Earlier works that propose constant throttling only keep the package/case tem ..."
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We derive analytically, the performance optimal throttling curve for a processor under thermal constraints for a given task sequence. We found that keeping the chip temperature constant requires an exponential speed curve. Earlier works that propose constant throttling only keep the package/case temperature constant, and are hence suboptimal. We develop highlevel thermal and power models that are simple enough for analysis, yet account for important effects like the powerdensity variation across a chip (hotspots), leakage dependence on temperature (LDT), and differing thermal characteristics of the silicon die and the thermal solution. We use a piecewiselinear approximation for the exponential leakage dependence on temperature, and devise a method to remove the circular dependency between leakage power and temperature. To solve the multitask speed control problem, we first solve analytically, the single task problem with a constraint on the final package temperature using optimal control theory. We then find the optimum final package temperature of each task by dynamic programming. We compared the total execution time of several randomly generated task sequences using the optimal control policy against a constant speed throttling policy, and found significantly smaller total execution times. We compared the thermal profiles predicted by the proposed highlevel thermal model to that of the Hotspot thermal model, and found them to be in good agreement.
Efficient online computation of core speeds to maximize the throughput of thermally constrained multicore processors
 In Proceedings of the International Conference on ComputerAided Design
, 2008
"... Abstract—We address the problem of efficient online computation of the speeds of different cores of a multicore processor to maximize the throughput (which is expressed as a weighted sum of the speeds), subject to an upper bound on the core temperatures. We first compute the solution for steadysta ..."
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Cited by 6 (0 self)
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Abstract—We address the problem of efficient online computation of the speeds of different cores of a multicore processor to maximize the throughput (which is expressed as a weighted sum of the speeds), subject to an upper bound on the core temperatures. We first compute the solution for steadystate thermal conditions by solving a linear program. We then present two approaches to computing the transient speed curves for each core: (i) a local solution, which involves solving a linear program every time step (of about 10 ms), and (ii) a global solution, which computes the optimal speed curve over a large time window (of about 100 s) by solving a nonlinear program. We showed that the local solution is insensitive to the weights assigned in the performance objective (hence the need for the global solution). This is because a reduction in the speed of a core can only reduce the temperature of the other cores over much larger time periods (of the order of several seconds). The local solution is then completely determined by the temperature constraint equations. We show that the constraint matrix exhibits a special property it can be expressed as the sum of a diagonal matrix and a matrix with identical rows. This allows us to solve the multicore thermal constraint equations analytically to determine the (temporally) local optimum speeds. Further, we showed that due to this property, the steadystate speed solution selects a set of threads to operate at maximum temperature, and turns off all unused cores. Hence, to ensure that all available threads are scheduled, we impose a “fairness ” constraint. Finally, we show how the openloop speed control methods proposed above could be used together with a feedback controller to achieve robustness to model uncertainty. I.
Frequency and Voltage Planning for MultiCore Processors Under Thermal Constraints
 in International Conference on Computer Design
"... Abstract — Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploiting the performance opportunities enabled by continued scaling, chip designers have migrated towards multicore architectures. Multico ..."
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Abstract — Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploiting the performance opportunities enabled by continued scaling, chip designers have migrated towards multicore architectures. Multicore architectures use multiple cores running at moderate clock frequencies to run several threads concurrently, which increases overall system throughput. In this work, we propose novel methods to find the optimal operating parameters, i.e., frequency and voltage, that maximize a multicore system throughput under thermal constraints. By adjusting core clock frequencies and voltages, onchip power dissipation can be spatially and temporally distributed to maximize the chip’s physical performance during runtime. We propose a simple, yet efficient model that accurately characterize the effects that changes in clock frequency and voltage have on onchip temperatures. Using the model, we find the optimal operating conditions for the following scenarios: (1) standard processor performance, where various cores operate using identical operating parameters, (2) optimal processor performance where each core can have its own frequency and voltage, and (3) optimal processor performance with thread priorities, where each core runs a thread of varied importance. We run several experiments across six different technology nodes to validate the work, assuring that our models and methods are accurate. Our methods demonstrate the total physical performance of a multicore system can be increased by up to 33.4 % without violating the maximum temperature constraints. I.
Performance Optimal Processor Throttling Under Thermal Constraints ∗
"... We derive analytically, the performance optimal throttling curve for a processor under thermal constraints for a given task sequence. We found that keeping the chip temperature constant requires an exponential speed curve. Earlier works that propose constant throttling only keep the package/case tem ..."
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We derive analytically, the performance optimal throttling curve for a processor under thermal constraints for a given task sequence. We found that keeping the chip temperature constant requires an exponential speed curve. Earlier works that propose constant throttling only keep the package/case temperature constant, and are hence suboptimal. We develop highlevel thermal and power models that are simple enough for analysis, yet account for important effects like the powerdensity variation across a chip (hotspots), leakage dependence on temperature (LDT), and differing thermal characteristics of the silicon die and the thermal solution. We use a piecewiselinear approximation for the exponential leakage dependence on temperature, and devise a method to remove the circular dependency between leakage power and temperature. To solve the multitask speed control problem, we first solve analytically, the single task problem with a constraint on the final package temperature using optimal control theory. We then find the optimum final package temperature of each task by dynamic programming. We compared the total execution time of several randomly generated task sequences using the optimal control policy against a constant speed throttling policy, and found significantly smaller total execution times. We compared the thermal profiles predicted by the proposed highlevel thermal model to that of the Hotspot thermal model, and found them to be in good agreement.
Performance Evaluation of 3D Stacked MultiCore Processors with Temperature Consideration
"... Abstract 3D stacked multicore processor is one of the applications of 3D integration technology. It achieves high bandwidth access to last level cache and allows to increase the number of cores while maintaining the package area. Although, 3D multicore temperature increases with the number of sta ..."
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Abstract 3D stacked multicore processor is one of the applications of 3D integration technology. It achieves high bandwidth access to last level cache and allows to increase the number of cores while maintaining the package area. Although, 3D multicore temperature increases with the number of stacked dies because of the escalating power density and thermal resistivity. Therefore, 3D multicores require lower clock frequencies for keeping the temperature under a safe constraint, so that performance is not always improved. In this paper, we evaluate the performance of 3D stacked multicores running under temperature constraints, and we show that there is a tradeoff between clock frequency and parallel capability. I.