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11
Implicit Enumeration of Strongly Connected Components
, 1999
"... This paper presents a BDDbased implicit algorithm to compute all maximal strongly connected components of directed graphs. The algorithm iteratively applies reachability analysis and sequentially identifies SCCs. Experiments suggest that the algorithm dramatically outperforms the only existing impl ..."
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Cited by 26 (0 self)
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This paper presents a BDDbased implicit algorithm to compute all maximal strongly connected components of directed graphs. The algorithm iteratively applies reachability analysis and sequentially identifies SCCs. Experiments suggest that the algorithm dramatically outperforms the only existing implicit method which must compute the transitive closure of the adjacencymatrix of the graphs.
Sequential Synthesis Using S1S
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2000
"... We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to problems arising in the synthesis and optimization of synchronous digital hardware. Specifically, we derive ..."
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Cited by 16 (7 self)
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We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to problems arising in the synthesis and optimization of synchronous digital hardware. Specifically, we derive a logical expression which yields a single finite state automaton characterizing the set of implementations that can replace a component of a larger design. The power of our approach is demonstrated by the fact that it generalizes immediately to arbitrary interconnection topologies, and to designs containing nondeterminism and fairness. We also describe control aspects of sequential synthesis and relate controller realizability to classical work on program synthesis and tree automata.
Formal Methods in VLSI System Design
, 1996
"... We apply mathematical logic to a number of problems arising in very large scale integration (VLSI) design automation. The first stage of this dissertation is concerned with techniques for the efficient verification of digital systems. We introduce heuristics based on Binary Decision Diagrams for eff ..."
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Cited by 4 (1 self)
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We apply mathematical logic to a number of problems arising in very large scale integration (VLSI) design automation. The first stage of this dissertation is concerned with techniques for the efficient verification of digital systems. We introduce heuristics based on Binary Decision Diagrams for efficiently representing designs specified as gatelevel circuits. We also present an approach to verifying hierarchical designs which uses novel notions of state equivalence to simplify components. The second stage addresses the problem of synthesizing digital designs. We use the logic S1S to demonstrate that the flexibility available for optimizing components in hierarchical designs can be characterized by a finite state automaton. This approach is extended to the problem of synthesizing p...
Optimizing Designs Containing Black Boxes
 34th Design Automation Conference
, 1997
"... We define a notion of equivalence for designs containing black boxes i.e., components whose functionality is not known; these arise naturally in the course of hierarchical design. Using this notion, we describe a sound and complete methodology for optimizing such designs. 1 ..."
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Cited by 3 (0 self)
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We define a notion of equivalence for designs containing black boxes i.e., components whose functionality is not known; these arise naturally in the course of hierarchical design. Using this notion, we describe a sound and complete methodology for optimizing such designs. 1
General Program Chairs Malay Ganai
, 2013
"... Aided Design Conference (FMCAD), and Formal Methods and Models for Codesign (MEMOCODE). The workshop emphasized the insightful experiences in tool and system design. The goal of the workshop is to provide a forum for sharing challenges and solutions that are original with ground breaking results. T ..."
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Aided Design Conference (FMCAD), and Formal Methods and Models for Codesign (MEMOCODE). The workshop emphasized the insightful experiences in tool and system design. The goal of the workshop is to provide a forum for sharing challenges and solutions that are original with ground breaking results. The workshop provided an opportunity for discussing engineering aspects and various design decisions required to put such formal tools and systems into practical use. It took a broad view of the formal tools/systems area, and solicited contributions from hardware and software domains such as decision procedures, verification, testing, validation, diagnosis, debugging, and synthesis. The workshop received 10 original submissions, out of which 3 were chosen under tool
AbstractionBased Livelock/Deadlock Checking for Hardware Verification
"... Livelock/deadlock is a well known and important problem in both hardware and software systems. In hardware verification, a livelock is a situation where the state of a design changes within only a smaller subset of the states reachable from the initial states of the design. Deadlock is a special cas ..."
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Livelock/deadlock is a well known and important problem in both hardware and software systems. In hardware verification, a livelock is a situation where the state of a design changes within only a smaller subset of the states reachable from the initial states of the design. Deadlock is a special case in which there is only one state in a livelock. However, livelock/deadlock checking has never been actively used in hardware verification in practice, mainly due to the complexity of the computation which involves finding strongly connected components. This paper presents a practical abstractionbased livelock/deadlock checking algorithm for hardware verification. The proposed livelock/deadlock checking works on FSMs rather than the whole design. For each FSM, we make an abstract machine of manageable size from the cone of influence machine, the livelock is justified on the concrete machine with trace concretization. Experimental results shows that the proposed abstractionbased livelock checking finds real livelock errors in industrial designs.
Verifying Designs Containing Black Boxes
, 1997
"... We define a notion of equivalence for designs containing black boxes. This notion is applicable to both gatelevel designs, as well as designs operating on integer variables. Using this notion, we describe a sound and complete methodology for optimizing designs containing black boxes, i.e. component ..."
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We define a notion of equivalence for designs containing black boxes. This notion is applicable to both gatelevel designs, as well as designs operating on integer variables. Using this notion, we describe a sound and complete methodology for optimizing designs containing black boxes, i.e. components whose functionality is not known; these arise naturally in the course of hierarchical design.
Optimizating Designs Containing Black Boxes
, 1997
"... We define a notion of equivalence for designs containing black boxes. Using this notion, we describe a sound and complete methodology for optimizing designs containing black boxes, i.e. components whose functionality is not known; these arise naturally in the course of hierarchical design. Keywords ..."
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We define a notion of equivalence for designs containing black boxes. Using this notion, we describe a sound and complete methodology for optimizing designs containing black boxes, i.e. components whose functionality is not known; these arise naturally in the course of hierarchical design. Keywords: Hierarchical Logic Synthesis, Black Boxes, Don't Cares 1 Introduction The advent of modern VLSI CAD tools has radically changed the process of designing digital systems. The first CAD tools automated the final stages of design, such as placement and routing. As the low level steps became better understood, the focus shifted to the higher stages. In particular logic synthesis, the science of optimizing gate level designs for measures such as area, speed, or power, has shifted to the forefront of CAD research. Logic synthesis algorithms originally targeted the optimization of PLA implementations [4]; this was followed by research in synthesizing more general multilevel logic implementations...
Microsoft
"... We study the problem of optimizing synchronous sequential circuits. There have been previous efforts to optimize such circuits. However, all previous attempts make implicit or explicit assumptions about the design or the environment of the design. For example, it is widespread practice to assume the ..."
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We study the problem of optimizing synchronous sequential circuits. There have been previous efforts to optimize such circuits. However, all previous attempts make implicit or explicit assumptions about the design or the environment of the design. For example, it is widespread practice to assume the existence of a hardware reset line and consequently a fixed powerup state; in the absence of the same, a common premise is that the design’s environment will apply an initializing sequence. We review the concept of safe replaceability which does away with these assumptions and the delaysafe replaceability notion, which is applicable when the design’s output is not used for a certain number of cycles after powerup. We then develop procedures for optimizing the combinational nextstate and output logic, as well as routines for reencoding the state space and removing state bits under these replaceability criteria. Experimental results demonstrate the effectiveness of our algorithms. Categories and Subject Descriptors: B.6.3 [Logic Design]: Design aids—Automatic synthesis