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47
An introduction to asynchronous circuit design
 THE ENCYCLOPEDIA OF COMPUTER SCIENCE AND TECHNOLOGY
, 1997
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RAPPID: An Asynchronous Instruction Length Decoder
, 1999
"... This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium Processor Instruction Decoder"), a prototype IA32 instruction length decoding and steering unit, ..."
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Cited by 63 (40 self)
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This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium Processor Instruction Decoder"), a prototype IA32 instruction length decoding and steering unit, was implemented using selftimed techniques. RAPPID chip was fabricated on a 0.25µ CMOS process and tested successfully. Results show significant advantagesin particular, performance of 2.54.5 instructions/nSwith manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400MHz clocked circuit.
Relative timing
 IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, 2003
"... Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (CElement, FIFO, and RAPPID Tag Unit), facilitating transformations from speedindependent circuits to burstmode, relative timed, and pulsemode circuits. Relative t ..."
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Cited by 39 (17 self)
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Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (CElement, FIFO, and RAPPID Tag Unit), facilitating transformations from speedindependent circuits to burstmode, relative timed, and pulsemode circuits. Relative timing enables improved performance, area, power and testability in all three cases. 1.
Verification of timed systems using POSETS
 In International Conference on Computer Aided Verification
, 1998
"... Abstract. This paper presents a new algorithm for efficiently verifying timed systems. The new algorithm represents timing information using geometric regions and explores the timed state space by considering partially ordered sets of events rather than linear sequences. This approach avoids the exp ..."
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Cited by 36 (11 self)
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Abstract. This paper presents a new algorithm for efficiently verifying timed systems. The new algorithm represents timing information using geometric regions and explores the timed state space by considering partially ordered sets of events rather than linear sequences. This approach avoids the explosion of timed states typical of highly concurrent systems by dramatically reducing the ratio of timed states to untimed states in a system. A general class of timed systems which include both event and level causality can be specified and verified. This algorithm is applied to several recent timed benchmarks showing orders of magnitude improvement in runtime and memory usage. 1
Efficient timing analysis algorithms for timed state space exploration
 In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, 1997
"... This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the synthesis procedure to optimize ..."
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Cited by 17 (9 self)
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This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the synthesis procedure to optimize the design. Much of the computational complexity in the synthesis of timed circuits currently is in finding the reachable timed state space. We introduce new algorithms which utilize geometric regions to represent the timed state space and partial orders to minimize the number of regions necessary. These algorithms operate on specifications sufficiently general to describe practical circuits. 1.
Timed State Space Exploration using POSETS
, 2000
"... This paper presents a new timing analysis algorithm for efficient state space exploration during the synthesis of timed circuits or the verification of timed systems. The source of the computational complexity in the synthesis or verification of a timed system is in finding the reachable timed state ..."
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Cited by 17 (9 self)
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This paper presents a new timing analysis algorithm for efficient state space exploration during the synthesis of timed circuits or the verification of timed systems. The source of the computational complexity in the synthesis or verification of a timed system is in finding the reachable timed state space. We introduce a new algorithm which utilizes geometric regions to represent the timed state space and partially ordered sets (POSETs) to minimize the number of regions necessary. This algorithm operates on specifications sufficiently general to describe practical circuits, as well as other timed systems. The algorithm is applied to several examples showing significant improvement in runtime and memory usage. I. Introduction The fundamental difficulty in circuit synthesis and verification is controlling the state explosion problem. The state spaces representing reasonably sized systems are large even if the timing behavior of the system is not considered. The problem gets even more c...
Timed Circuit Verification Using TEL Structures
 IEEE Transactions on ComputerAided Design of Integrated Circuits
, 2001
"... Abstract—Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In ord ..."
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Cited by 16 (6 self)
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Abstract—Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In order to automate the process of designing and verifying timed circuits, algorithms for their synthesis and verification are necessary. This paper presents timed event/level (TEL) structures, a specification formalism for timed circuits that corresponds directly to gatelevel circuits. It also presents an algorithm based on partially ordered sets to make the statespace exploration of TEL structures more tractable. The combination of the new specification method and algorithm significantly improves efficiency for gatelevel timing verification. Results on a number of circuits, including many from the recently published gigahertz unit Test Site (guTS) processor from IBM indicate that modules of significant size can be verified using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance. I.
Covering Conditions and Algorithms for the Synthesis of SpeedIndependent Circuits
 IEEE Transactions on ComputerAided Design
, 1998
"... This paper presents theory and algorithms for the synthesis of standard Cimplementations of speedindependent circuits. These implementations are blocklevel circuits which may consist of atomic gates to perform complex functions in order to ensure hazardfreedom. First, we present boolean covering ..."
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Cited by 14 (5 self)
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This paper presents theory and algorithms for the synthesis of standard Cimplementations of speedindependent circuits. These implementations are blocklevel circuits which may consist of atomic gates to perform complex functions in order to ensure hazardfreedom. First, we present boolean covering conditions that guarantee the standard Cimplementations operate correctly. Then, we present two algorithms that produce optimal solutions to the covering problem. The first algorithm is always applicable but does not complete on large circuits. The second algorithm, motivated by our observation that our covering problem can often be solved with a single cube, finds the optimal singlecube solution when such a solution exists. When applicable, the second algorithm is dramatically more efficient than the first, more general algorithm. We present results for benchmark specifications which indicate that our singlecube algorithm is applicable on most benchmark circuits and reduces runtimes by ...
Relative timing based verification of timed circuits and systems
 In Proc. International Workshop on Logic Synthesis
, 2002
"... Aggressive timed circuits, including synchronous and asynchronous selfresetting circuits, are particularly challenging to design and verify due to complicated timing constraints that must hold to ensure correct operation. Identifying a small, sufficient, and easily verifiable set of relative timing ..."
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Cited by 13 (4 self)
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Aggressive timed circuits, including synchronous and asynchronous selfresetting circuits, are particularly challenging to design and verify due to complicated timing constraints that must hold to ensure correct operation. Identifying a small, sufficient, and easily verifiable set of relative timing constraints simplifies both design and verification. However, the manual identification of these constraints is a complex and errorprone process. This paper presents the first systematic algorithm to generate and optimize relative timing constraints sufficient to guarantee correctness. The algorithm has been implemented in ourRTCG tool and has been applied to several reallife circuits. In all cases, the tool successfully generates a sufficient set of easily verifiable relative timing constraints. Moreover, the generated constraint sets are the same size or smaller than that of the handoptimized constraints. 1.
Hofstee. Verification of DelayedReset Domino Circuits using ATACS
 In 1999 International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU99
, 1999
"... This paper discusses the application of the timing analysis tool ATACS to the high performance, selfresetting and delayedreset domino circuits being designed at IBM’s Austin Research Laboratory. The tool, which was originally developed to deal with asynchronous circuits, is well suited to the self ..."
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Cited by 11 (2 self)
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This paper discusses the application of the timing analysis tool ATACS to the high performance, selfresetting and delayedreset domino circuits being designed at IBM’s Austin Research Laboratory. The tool, which was originally developed to deal with asynchronous circuits, is well suited to the selfresetting style since internally, a block of selfresetting or delayedreset domino logic is asynchronous. The circuits are represented using timed event/level structures. These structures correspond very directly to gate level circuits, making the translation from a transistor schematic to a TEL structure straightforward. The statespace explosion problem is mitigated using an algorithm based on partially ordered sets (POSETs). Results on a number of circuits from the recently published guTS (gigahertz unit Test Site) processor from IBM indicate that modules of significant size can be verified with ATACS using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance. 1