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124
Fixedoutline Floorplanning: Enabling Hierarchical Design
 IEEE Trans. on VLSI
, 2003
"... Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixedoutline floorplan formulation that is more relevant t ..."
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Cited by 113 (10 self)
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Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixedoutline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixedoutline floorplan problem are significantly harder than related instances of classical floorplan problems. We suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Wirelength improvements and optimization of aspect ratios of soft blocks are explicitly addressed by these techniques. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported [28]. A similar slack computation is possible with many other floorplan representations. In all cases the computation time approximately doubles. Our empirical evaluation is based on a new floorplanner implementation Parquet1 that can operate in both outlinefree and fixedoutline modes. We use Parquet1 to floorplan a design, with approximately 32000 cells, in 37 min using a topdown, hierarchical paradigm.
Decoupling Capacitance Allocation and Its Application to PowerSupply NoiseAware Floorplanning
 IEEE Trans. ComputerAided Design
, 2002
"... Abstract—We investigate the problem of decoupling capacitance (decap) allocation for power supply noise suppression at floorplan level. First, we assume that a floorplan is given and consider the decap placement as a postfloorplan step. Second, we consider the decap placement as an integral part of ..."
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Cited by 63 (5 self)
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Abstract—We investigate the problem of decoupling capacitance (decap) allocation for power supply noise suppression at floorplan level. First, we assume that a floorplan is given and consider the decap placement as a postfloorplan step. Second, we consider the decap placement as an integral part of a floorplanning methodology (noiseaware floorplanning). In both cases, the objective is to minimize the floorplan area while suppressing the power supply noise below the specified limit. Experimental results on MCNC benchmark circuits show that, for postfloorplan decap placement, the white space allocated for decap is about 6%–9 % of the chip area for the 0.25 m technology. The powersupply noise is kept below the specified limit. Compared to postfloorplan approach, the peak powersupply noise can be reduced by as much as 40% and the decap budget can be reduced by as much as 21 % by using noiseaware floorplanning methodology. The total area is also reduced due to the reduced total decap budget gained from reduced power supply noise. Index Terms—Decoupling capacitance, floorplan, power supply noise. I.
Fixedoutline Floorplanning Through Better Local Search
 IN PROC. INTERNATIONAL CONFERENCE ON COMPUTER DESIGN
, 2001
"... Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice of moves is fairly straightforward. In this work, ..."
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Cited by 56 (4 self)
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Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice of moves is fairly straightforward. In this work,
Consistent Placement of MacroBlocks Using Floorplanning and StandardCell Placement
 AND STANDARDCELL PLACEMENT”, ISPD 2002
, 2002
"... While a number of recent works address largescale standardcell placement, they typically assume that all macros are fixed. Floorplanning techniques are very good at handling macros, but do not scale to hundreds of thousands of placeable objects. Therefore we combine floorplanning techniques with p ..."
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Cited by 55 (9 self)
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While a number of recent works address largescale standardcell placement, they typically assume that all macros are fixed. Floorplanning techniques are very good at handling macros, but do not scale to hundreds of thousands of placeable objects. Therefore we combine floorplanning techniques with placement techniques in a design flow that solves the more general placement problem. Our work shows how to place macros consistently with large numbers of small standard cells. Our techniques can also be used to guide circuit designers who prefer to place macros by hand. The proposed
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
, 2007
"... In this paper, we present FastPlace 3.0 – an efficient and scalable multilevel quadratic placement algorithm for largescale mixedsize designs. The main contributions of our work are: (1) A multilevel global placement framework, by incorporating a twolevel clustering scheme within the flat analyt ..."
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Cited by 38 (9 self)
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In this paper, we present FastPlace 3.0 – an efficient and scalable multilevel quadratic placement algorithm for largescale mixedsize designs. The main contributions of our work are: (1) A multilevel global placement framework, by incorporating a twolevel clustering scheme within the flat analytical placer FastPlace [27, 28]. (2) An efficient and improved Iterative Local Refinement technique that can handle placement blockages and placement congestion constraints. (3) A congestion aware standardcell legalization technique in the presence of blockages. On the ISPD2005 placement benchmarks [19], our algorithm is 5.12×, 11.52 × and 16.92 × faster than mPL6, Capo10.2 and APlace2.0 respectively. In terms of wirelength, we are on average,
Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation
, 2000
"... of block placement called sequence pair. All block placement algorithms which are based on sequence pairs use simulated annealing where the generation and evaluation of a large number of sequence pairs is required. Therefore, a fast algorithm is needed to evaluate each generated sequence pair, i.e. ..."
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Cited by 33 (3 self)
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of block placement called sequence pair. All block placement algorithms which are based on sequence pairs use simulated annealing where the generation and evaluation of a large number of sequence pairs is required. Therefore, a fast algorithm is needed to evaluate each generated sequence pair, i.e. to translate the sequence pair to its corresponding block placement. This paper presents a new approach to evaluate a sequence pair based on computing longest common subsequence in a pair of weighted sequences. We present a very simple and problem. We also show that using a more sophisticated in [1]. For example, we achieve 60X speedup over the previous algorithm when input size n # ###.
Multilevel placement for largescale mixedsize IC designs
 In Proc. Asia and South Pacific Design Automation Conf
, 2003
"... Abstract — In this paper we study the largescale mixedsize placement problem where there is a significant size variation between big and small placeable objects (the ratio can be as large as 10,000). We develop a multilevel optimization algorithm, MPGMS, for this problem which can efficiently ha ..."
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Cited by 33 (3 self)
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Abstract — In this paper we study the largescale mixedsize placement problem where there is a significant size variation between big and small placeable objects (the ratio can be as large as 10,000). We develop a multilevel optimization algorithm, MPGMS, for this problem which can efficiently handle both largescale designs and large size variations. Compared with the recently published work [1] on largescale mixed macro and standard cell placement benchmarks for wirelength minimization, our method can achieve 13 % wirelength reduction on average with comparable runtime.
Bin packing in multiple dimensions: Inapproximability results and approximation schemes
 MATHEMATICS OF OPERATIONS RESEARCH
, 2006
"... We study the multidimensional generalization of the classical Bin Packing problem: Given a collection of ddimensional rectangles of specified sizes, the goal is to pack them into the minimum number of unit cubes. A long history of results exists for this problem and its special cases. Currently, t ..."
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Cited by 30 (7 self)
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We study the multidimensional generalization of the classical Bin Packing problem: Given a collection of ddimensional rectangles of specified sizes, the goal is to pack them into the minimum number of unit cubes. A long history of results exists for this problem and its special cases. Currently, the best known approximation algorithm for packing twodimensional rectangles achieves a guarantee of 1.69 in the asymptotic case (i.e., when the optimum uses a large number of bins) [3]. An important open question has been whether 2−dimensional bin packing is essentially similar to the 1−dimensional case in that it admits an asymptotic polynomial time approximation scheme (APTAS) [12, 17] or not. We answer the question in the negative and show that the problem is APX hard in the asymptotic sense. On the positive side, we give the following results: First, we consider the special case where we have to pack ddimensional cubes into the minimum number of unit cubes. We give an asymptotic polynomial time approximation scheme for this problem. This represents a significant improvement over the previous best known asymptotic approximation factor of 2 − (2/3) d [21] (1.45 for d = 2 [11]), and settles the approximability of the problem. Second, we give a polynomial time algorithm for packing arbitrary rectangles into at most OPT square bins with sides of length 1 + ε, where OPT denotes the minimum number of unit bins required to pack these rectangles. Interestingly, this result does not have an additive constant term i.e., is not an asymptotic result. As a corollary, we obtain a polynomial time approximation scheme for the problem of placing a collection of rectangles in a minimum area encasing rectangle, settling also the approximability of this problem.
Combinatorial Techniques for Mixedsize Placement
 ACM TRANS. ON DESIGN AUTOM. OF ELEC. SYS
, 2005
"... ..."
Floorplanning Optimization with Trajectory PiecewiseLinear Model for Pipelined Interconnects
 in Proc. ACM Design Automation Conf
, 2004
"... Interconnect pipelining has a great impact on system performance, but has not been considered by automatic floorplanning. Considering interconnect pipelining, we study the floorplanning optimization problem to minimize system CPI (cycles per instruction) and in turn maximize system performance. We d ..."
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Cited by 19 (3 self)
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Interconnect pipelining has a great impact on system performance, but has not been considered by automatic floorplanning. Considering interconnect pipelining, we study the floorplanning optimization problem to minimize system CPI (cycles per instruction) and in turn maximize system performance. We develop an efficient tablebased model called trajectory piecewise linear (TPWL) model to estimate CPI with interconnect pipelining. Experiments show that the TPWL model differs from cycleaccurate simulations by less than 3.0%. We integrate this model with a simulatedannealing based floorplan optimization to obtain CPIaware floorplanning. Compared to the conventional floorplanning to minimize area and wire length, our CPIaware floorplanning can reduce CPI by up to 28.6% with a small area overhead of 5.69% under 100nm technology and obtain better results under 70nm technology. To the best of our knowledge, this paper is the first indepth study on floorplanning optimization with consideration of interconnect pipelining.