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17
CMP Fill Synthesis: A Survey of Recent Studies
, 2008
"... We survey recent research and practice in the area of chemical–mechanical polishing (CMP) fill synthesis, in terms of both problem formulations and solution approaches. We review the CMP as the planarization technique of choice for multilevel very largescale integration metallization processes. Po ..."
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Cited by 8 (1 self)
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We survey recent research and practice in the area of chemical–mechanical polishing (CMP) fill synthesis, in terms of both problem formulations and solution approaches. We review the CMP as the planarization technique of choice for multilevel very largescale integration metallization processes. PostCMP wafer topography varies according to pattern density. We review densityanalysis methods and densitycontrol objectives that are used in today’s fillsynthesis algorithms. In addition, we discuss the concept of designdriven fill synthesis that seeks to optimize CMP fill with respect to objectives beyond mere density uniformity. Designdriven fill synthesis minimizes the impact of CMP fill on design performance and parametric yield while still satisfying the density criteria that are motivated by manufacturing models. We conclude with a discussion of where CMP fill synthesis may be naturally integrated within future design and manufacturing flows.
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations
"... Abstract — This paper solves the variationaware onchip decoupling capacitance (decap) budgeting problem. Unlike previous work assuming the worstcase current load, we develop a novel stochastic current model, which efficiently and accurately captures operation variation such as temporal correlatio ..."
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Cited by 7 (6 self)
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Abstract — This paper solves the variationaware onchip decoupling capacitance (decap) budgeting problem. Unlike previous work assuming the worstcase current load, we develop a novel stochastic current model, which efficiently and accurately captures operation variation such as temporal correlation between clock cycles and logicinduced correlation between ports. The models also considers current variation due to process variation with spatial correlation. We then propose an iterative alternative programming algorithm to solve the decap budgeting problem under the stochastic current model. Experiments using industrial examples show that compared with the baseline model which assumes maximum currents at all ports and under the same decap area constraint, the model considering temporal correlation reduces the noise by up to 5×, and the model considering both temporal and logicinduced correlations reduces the noise by up to 17×. Compared with the model using deterministic process parameters, considering process variation (Leff variation in this paper) reduces the mean noise by up to 4× and the 3σ noise by up to 13×. While the existing stochastic optimization has been used mainly for process variation purpose, this paper to the best of our knowledge is the first indepth study on stochastic optimization taking into account both operation and process variations for power network design. We convincingly show that considering operation variation is highly beneficial for power integrity optimization and this should be researched for optimizing signal and thermal integrity as well. I.
VariabilityDriven Buffer Insertion Considering Correlations
, 2005
"... In this work we consider the buffer insertion problem under manufacturing variability. Variability in effect randomizes design parameters which in practice are correlated to each other. We propose a probabilistic buffer insertion method assuming variations on both interconnect and buffer parameters ..."
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Cited by 5 (0 self)
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In this work we consider the buffer insertion problem under manufacturing variability. Variability in effect randomizes design parameters which in practice are correlated to each other. We propose a probabilistic buffer insertion method assuming variations on both interconnect and buffer parameters and considering correlations. We have shown that ignoring correlations results in overestimation of delay paths resulting in suboptimal solution. Our proposed method is compatible with more accurate net delay model of [1] as well as the Elmore delay model. In addition effective probabilistic pruning criteria is proposed that considers correlations among potential solutions. Experimental results on a group of selected nets show superiority of our approach. Considering correlations using delay model in [1] results in probability of meeting the required time constraint of on average 63.0%. Probabilistic buffer insertion ignoring correlations and traditional deterministic approaches, results in on average 25.4% and 18.8% respectively.
VCTA: A viaconfigurable transistor array regular fabric
 in VLSI System on Chip Conference (VLSISoC), 2010 18th IEEE/IFIP
, 2010
"... Abstract—Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called ViaConfigurable T ..."
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Abstract—Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called ViaConfigurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Our objective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for CarryRipple Adders from 4 bits to 64 bits.
Robust Gate Sizing via Mean Excess Delay Minimization
, 2008
"... We introduce mean excess delay as a statistical measure of circuit delay in the presence of parameter variations. The βmean excess delay is defined as the expected delay of the circuits that exceed the βquantile of the delay, so it is always an upper bound on the βquantile. However, in contrast t ..."
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We introduce mean excess delay as a statistical measure of circuit delay in the presence of parameter variations. The βmean excess delay is defined as the expected delay of the circuits that exceed the βquantile of the delay, so it is always an upper bound on the βquantile. However, in contrast to the βquantile, it preserves the convexity properties of the underlying delay distribution. We apply the βmean excess delay to the circuit sizing problem, and use it to minimize the delay quantile over the gate sizes. We use the Analytic Centering Cutting Plane Method to perform the minimization and apply this sizing to the ISCAS ‘85 benchmarks. Depending on the structure of the circuit, it can make significant improvements on the 95%quantile.
Design of IntegratedCircuit Interconnects with Accurate Modeling of ChemicalMechanical Planarization
"... Dummy fill insertion in Chemicalmechanical Planarization (CMP) can change the coupling and total capacitance of interconnect. Moreover, dishing and erosion phenomena change interconnect crosssections and hence significantly affect interconnect resistance. This work first studies interconnect para ..."
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Dummy fill insertion in Chemicalmechanical Planarization (CMP) can change the coupling and total capacitance of interconnect. Moreover, dishing and erosion phenomena change interconnect crosssections and hence significantly affect interconnect resistance. This work first studies interconnect parasitic variations due to (1) different fill patterns that are nominally “equivalent ” with respect to foundry rules; and (2) dishing and erosion of conductors and dielectric using an accurate densitystepheight model for multistep CMP from the literature.1 Our results show that for long parallel wires the variation of coupling capacitance between adjacent wires can be up to 25 % and 300 % for wires that are 3x and 6x minimum space apart respectively, and the variation of total wire capacitance can be more than 10%. We also show that the variation of wire resistance due to dishing and erosion can be over 30%. This work also evaluates how CMP effects (fill insertion, dishing and erosion) impact the achievable delay of buffered global onchip interconnects. We obtain the delay of buses from accurate SPICE simulations considering CMPrelated parasitic variation. Our studies show that the interconnect design considering fill and buffer insertion simultaneously with CMP effects reduces the unit length delay of global interconnect bus by up to 3.3 % over the design which does not consider any CMP effects. 1.
An UltraLowEnergy, VariationTolerant FPGA Architecture Using ComponentSpecific Mapping
, 2013
"... iii As feature sizes scale toward atomic limits, parameter variation continues to increase, leading to increased margins in both delay and energy. Parameter variation both slows down devices and causes devices to fail. For applications that require high performance, the possibility of very slow devi ..."
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iii As feature sizes scale toward atomic limits, parameter variation continues to increase, leading to increased margins in both delay and energy. Parameter variation both slows down devices and causes devices to fail. For applications that require high performance, the possibility of very slow devices on critical paths forces designers to reduce clock speed in order to meet timing. For an important and emerging class of applications that target energyminimal operation at the cost of delay, the impact of variationinduced defects at very low voltages mandates the sizing up of transistors and operation at higher voltages to maintain functionality. With postfabrication configurability, FPGAs have the opportunity to selfmeasure the impact of variation, determining the speed and functionality of each individual resource. Given that information, a delayaware router can use slow devices on noncritical paths, fast devices on critical paths, and avoid known defects. By mapping each component individually and customizing designs to a component’s unique physical characteristics, we demonstrate that we can eliminate delay margins and reduce energy margins caused by variation.
8 Stochastic Optimization Over Correlated Data Set: A Case Study on VLSI Decoupling Capacitance Budgeting
"... It is very common in engineering society to optimize certain objective functions under the worst scenario among a set of possible scenarios, i.e., minx maxi f (x) s.t. x ∈ S(pi), i = 1, 2,..., (1) ..."
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It is very common in engineering society to optimize certain objective functions under the worst scenario among a set of possible scenarios, i.e., minx maxi f (x) s.t. x ∈ S(pi), i = 1, 2,..., (1)