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FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in LookupTable Based FPGA Designs
 IEEE TRANS. CAD
, 1994
"... The field programmable gatearray (FPGA) has become an important technology in VLSI ASIC designs. In the past a few years, a number of heuristic algorithms have been proposed for technology mapping in lookuptable (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Bo ..."
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Cited by 317 (41 self)
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The field programmable gatearray (FPGA) has become an important technology in VLSI ASIC designs. In the past a few years, a number of heuristic algorithms have been proposed for technology mapping in lookuptable (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean networks and little is known about how far their solutions are away from the optimal ones. This paper presents a theoretical breakthrough which shows that the LUTbased FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time. A key step in our algorithm is to compute a minimum height Kfeasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUTs by maximizing the volume of each cut and by several postprocessing operations. Based on these results, we have implemented an LUTbased FPGA mapping package called FlowMap. We have tested FlowMap on a large set of benchmark examples and compared it with other LUTbased FPGA mapping algorithms for delay optimization, including Chortled, MISpgadelay, and DAGMap. FlowMap reduces the LUT network depth by up to 7% and reduces the number of LUTs by up to 50% compared to the three previous methods.
On Area/Depth Tradeoff in LUTBased FPGA Technology Mapping
 IEEE Trans. on VLSI Systems
, 1994
"... In this paper we study the area and depth tradeoff in LUT based FPGA technology mapping. Starting from a depthoptimal mapping solution, we perform a number of depth relaxation operations to obtain a new network with bounded increase in depth and advantageous to subsequent remapping for area minim ..."
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Cited by 73 (23 self)
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In this paper we study the area and depth tradeoff in LUT based FPGA technology mapping. Starting from a depthoptimal mapping solution, we perform a number of depth relaxation operations to obtain a new network with bounded increase in depth and advantageous to subsequent remapping for area minimization. We then remap the resulting network to obtain an areaminimized mapping solution. By gradually increasing the depth bound, for each design we are able to produce a set of mapping solutions with smooth area and depth tradeoff. For the area minimization step, we have developed an optimal algorithm for computing an areaminimum mapping solution without node duplication. Experimental results show that our solution sets outperform the solutions produced by many existing mapping algorithms in terms of both area and depth minimization. 1. Introduction The Field programmable gate array (FPGA) has become a very popular technology in VLSI ASIC design and system prototyping. The lookup tabl...
Cut Ranking and Pruning: Enabling A General And Efficient FPGA Mapping Solution
 Proc. FPGA `99
, 1999
"... Cut enumeration is a common approach used in a number of FPGA synthesis and mapping algorithms for consideration of various possible LUT implementations at each node in a circuit. Such an approach is very general and flexible, but often suffers high computational complexity and poor scalability. In ..."
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Cited by 62 (10 self)
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Cut enumeration is a common approach used in a number of FPGA synthesis and mapping algorithms for consideration of various possible LUT implementations at each node in a circuit. Such an approach is very general and flexible, but often suffers high computational complexity and poor scalability. In this paper, we develop several efficient and effective techniques on cut enumeration, ranking and pruning. These techniques lead to much better runtime and scalability of the cutenumeration based algorithms; they can also be used to compute a tight lowerbound on the size of an areaminimum mapping solution. For areaoriented FPGA mapping, experimental results show that the new techniques lead to over 160X speedup over the original optimal duplicationfree mapping algorithm, achieve mapping solutions with 521% smaller area for heterogeneous FPGAs compared to those by Chortlecrf [6], MISpganew [9], and TOSTUM [4], yet with over 100X speedup over MISpganew [9] and TOSTUM [4]. 1 Intr...
DAOmap: A depthoptimal area optimization mapping algorithm for FPGA designs
 Proc. ICCAD ’04
, 2004
"... In thispaper we study the technology mappingproblem for FPGA architectures to minimize chip area, or the total number of lookup tables (LlJTs) ofthe mapped design, under the chip performance constraint. This is a wellstudied topic and a very diflcult task (NPhard) The contributions of this paper a ..."
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Cited by 61 (12 self)
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In thispaper we study the technology mappingproblem for FPGA architectures to minimize chip area, or the total number of lookup tables (LlJTs) ofthe mapped design, under the chip performance constraint. This is a wellstudied topic and a very diflcult task (NPhard) The contributions of this paper are as Jollaws: (i) we consider the potential node duplications during the CUI enumeration/generotion procedure so the mapping costs encoded in the cuts drive the areaoptimization objective more effectively: (iij affer the timing constraint is determined, we will relax the noncritical paths by searching the solution space considering both local andglobal optimality information to minimize mapping area; (iiij an iterative cut selection procedure is carried out that further explores and perturbs the solution space to improve solution quality. We guarantee optimal mapping depth under the unit delay model. Experimental results show that our mapping algorithm, named DAOmap, produces significant quality and runtime improvements. Compared to the stoteo/theart depthoptimal, area minimization mapping algorithm CutMap [21], DAOmap is 16.02 % better on area and runs 24.2X faster on average when both algorithms are mapping to FPGAs using LWs oJfive inputs. LUTs of other inputs are also used for comparisons.
A New Method to Express Functional Permissibilities for LUT based FPGAs and Its Applications
 In International Conference on Computer Aided Design, p. 254 – 261
, 1996
"... This paper presents a new method to express functional permissibilities for lookup table (LUT) based field programmable gate arrays (FPGAs). The method represents functional permissibilities by using sets of pairs of functions, not by incompletely specified functions. It makes good use of the prope ..."
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Cited by 49 (5 self)
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This paper presents a new method to express functional permissibilities for lookup table (LUT) based field programmable gate arrays (FPGAs). The method represents functional permissibilities by using sets of pairs of functions, not by incompletely specified functions. It makes good use of the properties of LUTs such that their internal logics can be freely changed. The permissibilities expressed by the proposed method have the desired property that at many points of a network they can be simultaneously treated. Applications of the proposed method are also presented; a method to optimize networks and a method to remove connections that are obstacles at the routing step. Preliminary experimental results are given to show the effectiveness of our proposed method. 1 Introduction Because of their low cost, reprogrammability and rapid turnaround times, field programmable gate arrays (FPGAs) have emerged as an attractive means to implement low volume applications and prototypes[1]. FPGAs ...
Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays
 ACM Transactions on Design Automation of Electronic Systems
, 1996
"... The increasing popularity of the field programmable gatearray (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGAspecific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a Ki ..."
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Cited by 35 (11 self)
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The increasing popularity of the field programmable gatearray (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGAspecific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a Kinput oneoutput lookuptable (LUT) that can implement any Boolean function of up to K variables. This unique feature of the LUT has brought new challenges to logic synthesis and optimization, resulting in many new techniques reported in recent years. This article summarizes the research results on combinational logic synthesis for LUT based FPGAs under a coherent framework. These results were dispersed in various conference proceedings and journals and under various formulations and terminologies. We first present general problem formulations, various optimization objectives and measurements, then focus on a set of commonly used basic concepts and techniques, and finally summarize existing synthesis algorithms and systems. We classify and summarize the basic techniques into two categories, namely, logic optimization and technology mapping, and describe the existing algorithms and systems in terms of how they use the classified basic
Segmented Routing for SpeedPerformance and Routability in FieldProgrammable Gate Arrays
 Journal of VLSI Design
, 1996
"... This paper addresses several issues involved for routing in FieldProgrammable Gate Arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measurin ..."
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Cited by 28 (2 self)
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This paper addresses several issues involved for routing in FieldProgrammable Gate Arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A twostage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speedperformance of implemented circuits. The experiments presented in this paper address both of the key metrics for FPGA routing tools, namely the eff...
Heuristics for area minimization in LUTbased FPGA technology mapping
 Proc. IWLS ’04
, 2004
"... In this paper, an iterative technology mapping tool called IMap is presented. It supports depthoriented (area is a secondary objective), areaoriented (depth is a secondary objective), and duplicationfree mapping modes. The edge delay model, as opposed to the more common unit delay model, is used ..."
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Cited by 24 (5 self)
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In this paper, an iterative technology mapping tool called IMap is presented. It supports depthoriented (area is a secondary objective), areaoriented (depth is a secondary objective), and duplicationfree mapping modes. The edge delay model, as opposed to the more common unit delay model, is used throughout. Two new heuristics are used to obtain area reductions over previously published methods. The first heuristic predicts the effects of various mapping decisions on the area of the final solution and the second heuristic bounds the depth of the mapping solution at each node. In depthoriented mode, when targeting 5LUTs, IMap obtains depth optimal solutions that are 13.3 % and 12.5 % smaller than those produced by CutMAP and FlowMAPr0, respectively. Targetting the same LUT size in areaoriented mode, IMap obtains solutions that are 13.7 % smaller than those produced by duplicationfree mapping. 1.
Logic synthesis for lookup table based FPGAs using functional decomposition and support minimization
 In Proc. ICCAD
, 1995
"... This paper presents a logic synthesis method for lookup table (LUT) based eld programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition. We use not only disjunctive decomposition but also nondisjunctive decomposition. Furthermore, we propose a new B ..."
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Cited by 23 (4 self)
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This paper presents a logic synthesis method for lookup table (LUT) based eld programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition. We use not only disjunctive decomposition but also nondisjunctive decomposition. Furthermore, we propose a new Boolean resubstitution technique customized for an LUT network synthesis. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share the common function among two or more functions. The Boolean resubstitution is eectively carried out by solving a support minimization problem for an incompletely specied function. We can also handle satisability don't cares of an LUT network using the technique. 1
OBDDbased function decomposition: Algorithms and implementation
 IEEE Transactions on ComputerAided Design of Integrated Ciruits and Systems
, 1996
"... 2 An example of disjunctive decomposition.::::::::::::::::::::: 33 3 An example of nondisjunctive decomposition.::::::::::::::::::: 34 4 An example for operator cut vector.:::::::::::::::::::::::: 35 5 An example of multipleoutput decomposition in OBDD representation.:::::: 36 6 The Xilinx XC4000 C ..."
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Cited by 21 (0 self)
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2 An example of disjunctive decomposition.::::::::::::::::::::: 33 3 An example of nondisjunctive decomposition.::::::::::::::::::: 34 4 An example for operator cut vector.:::::::::::::::::::::::: 35 5 An example of multipleoutput decomposition in OBDD representation.:::::: 36 6 The Xilinx XC4000 CLB.::::::::::::::::::::::::::::: 37