Design and IsoArea Vmin Analysis of 9T Sub-threshold SRAM With BitInterleaving Scheme in 65-nm CMOS,” IEEE trans. on ckt (2012)

by Ming-Hung Chang, Yi-Te Chiu, Wei Hwang
Venue:Kilakarai in April 2000 and M.E(VLSI Design) from Adhiparasakthi Engineering College, Melmaruvathur in June 2011. She is now with Sastha Institute of Engineering and Technology