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The design and evaluation of hierarchical multi-level parallelisms for H.264 encoder on multi-core architecture. (2010)

by H Wei, J Yu, J Li
Venue:Comput. Sci. Inf. Syst.,
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Network for Sustainable Ultrascale Computing Efficient Parallel Video Encoding on Heterogeneous Systems

by Nesus First , Workshop
"... Abstract In this study we propose an efficient method for collaborative H.264/AVC inter-loop encoding in heterogeneous CPU+GPU systems. This method relies on specifically developed extensive library of highly optimized parallel algorithms for both CPU and GPU architectures, and all inter-loop modul ..."
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Abstract In this study we propose an efficient method for collaborative H.264/AVC inter-loop encoding in heterogeneous CPU+GPU systems. This method relies on specifically developed extensive library of highly optimized parallel algorithms for both CPU and GPU architectures, and all inter-loop modules. In order to minimize the overall encoding time, this method integrates adaptive load balancing for the most computationally intensive, inter-prediction modules, which is based on dynamically built functional performance models of heterogenous devices and inter-loop modules. The proposed method also introduces efficient communication-aware techniques, which maximize data reusing, and decrease the overhead of expensive data transfers in collaborative video encoding. The experimental results show that the proposed method is able of achieving real-time video encoding for very demanding video coding parameters, i.e., full HD video format, 64Ă—64 pixels search area and the exhaustive motion estimation.
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...ls search area (SA) on a commodity desktop platform equipped with a multi-core CPU and two GPUs. To the best of the authors’ knowledge, this is one of the first approaches that applies adaptive load balancing with dynamically built partial estimations of the FPMs to tackle efficient collaborative execution of complex multi-module problems, such as video encoding, in heterogenous environments. II. Related Work There are only few state-of-the-art approaches that deal with the efficient parallel implementation of the entire video encoder (or its main functional parts), namely, for multi-core CPU [21], GPU [22], or CPU+GPU [14, 15] environments. In CPU+GPU systems, these approaches either i) simply offload a single inter-loop module in its entirety (mainly the ME) to the GPU, while performing the rest of the encoder on the CPU [9,19], or ii) exploit simultaneous CPU+GPU processing at the level of a single inter-loop module [15, 23]. These approaches have a limited scalability (only one GPU can be employed) and cannot fully exploit the capabilities of CPU+GPU systems (since the CPU is idle, while the GPU processes the entire offloaded module) [19]. In [9] the pipelining granularity is decid...

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