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ADELTA: A 64bit High Speed, Compact, Hybrid DynamicCMOS/ThresholdLogic Adder
"... A high speed 64bit dynamic adder, the AdelaideDelft Threshold Logic Adder (ADELTA), is presented. The adder is based on a hybrid carrylookahead/carryselect scheme using threshold logic and conventional CMOS logic. ADELTA was designed and simulated in a 0.35 m process. The worst case critic ..."
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A high speed 64bit dynamic adder, the AdelaideDelft Threshold Logic Adder (ADELTA), is presented. The adder is based on a hybrid carrylookahead/carryselect scheme using threshold logic and conventional CMOS logic. ADELTA was designed and simulated in a 0.35 m process. The worst case critical path latency is 670 ps, which is shown to be on average 30% faster than previously proposed high speed Boolean dynamic logic adders while at the same time reducing the transistor count on average by over 30% compared to the same adders.
Area efficient, high speed parallel counter circuits using charge recycling threshold logic
 In Proc. IEEE International Symposium on Circuits and Systems
, 2003
"... The main result is the development of a low depth, highly compact implementation of parallel counters (i.e., population counters), based on threshold logic. Two such counters are designed using the recently proposed Charge Recycling Threshold Logic (CRTL) gate. The novel feature of the designs is th ..."
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The main result is the development of a low depth, highly compact implementation of parallel counters (i.e., population counters), based on threshold logic. Two such counters are designed using the recently proposed Charge Recycling Threshold Logic (CRTL) gate. The novel feature of the designs is the sharing among all threshold gates of a single capacitive network for computing the weighted sum of all input bits. The significance of the result is the reduction by almost 35 % in the required number of capacitors for the (7,3) counter and by over 60 % for the (15,4) counter. This reduces the total area by approximately 37 % for the (7,3) counter and by 60 % for the (15,4) counter, with no increase in delay. The proposed (7,3) counter design is also shown to be 45 % faster compared to a conventional Boolean fulladder based circuit. 1.
StateoftheArt in CMOS ThresholdLogic VLSI Gate Implementations and Applications
"... In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in CMOS. This paper presents a summary of the recent developments in TL circuit design. Highperformance TL gate circuit implementatio ..."
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In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in CMOS. This paper presents a summary of the recent developments in TL circuit design. Highperformance TL gate circuit implementations are compared, and a number of their applications in computer arithmetic operations are reviewed. It is shown that the application of TL in computer arithmetic circuit design can yield designs with signi cantly reduced transistor count and area while at the same time reducing circuit delay and power dissipation when compared to conventional CMOS logic.
νMOS Enhanced Differential CurrentSwitch Threshold
"... Abstract — This paper presents a way to enhance the Differential CurrentSwitch Threshold Logic gate (DCSTL) in order to allow the gate to perform more complex functions. This enhancement is achieved by replacing the MOStransistors at the data and threshold mapping bank of the DCSTL gate with neur ..."
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Abstract — This paper presents a way to enhance the Differential CurrentSwitch Threshold Logic gate (DCSTL) in order to allow the gate to perform more complex functions. This enhancement is achieved by replacing the MOStransistors at the data and threshold mapping bank of the DCSTL gate with neuronMOS transisors. First, we introduce the neuronMOSenhanced DCSTL gate. Then, the results of HSPICE simulations of a 7input parity and a 3bit addition function implemented with the enhanced DCSTL gate is presented, along with a comparison with the same functions implemented using the original DCSTL gate. These simulations indicate that the designs based on enhanced DCSTL gates can achieve a 12.5 % speedup over the conventional DCSTL gate designs for both addition and parity. HSPICE power estimations also suggest that the standard DCSTL gate dissipates 30 % more power when performing a 7bit parity, and 5 % in the case of a 3bit addition. Keywords—Threshold logic, neuronMOS transistors, parity, addition I.