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13
TCGS: Orthogonal Coupling of P*admissible Representations for General Floorplans
 IN PROCEEDINGS OF THE DESIGN AUTOMATION CONFERENCE
, 2002
"... We extend in this paper the concept of the Padmissible floorplan representation to that of the P*admissible one. A P*admissible representation can model the most general floorplans. Each of the currently existing P*admissible representations, SP, BSG, and TCG, has its strengths as well as weakne ..."
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Cited by 14 (3 self)
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We extend in this paper the concept of the Padmissible floorplan representation to that of the P*admissible one. A P*admissible representation can model the most general floorplans. Each of the currently existing P*admissible representations, SP, BSG, and TCG, has its strengths as well as weaknesses. We show the equivalence of the two most promising P*admissible representations, TCG and SP, and integrate TCG with a packing sequence (part of SP) into a new representation, called TCGS. TCGS combines the advantages of SP and TCG and at the same time eliminates their disadvantages. With the property of SP, faster packing and perturbation schemes are possible. Inherited nice properties from TCG, the geometric relations among modules are transparent to TCGS (implying faster convergence to a desired solution), placement with position constraints becomes much easier, and incremental update for cost evaluation can be realized. These nice properties make TCGS a superior representation which exhibits an elegant solution structure to facilitate the search for a desired floorplan/placement. Extensive experiments show that TCGS results in the best area utilization, wirelength optimization, convergence speed, and stability among existing works and is very flexible in handling placement with special constraints.
Floorplan and power/ground network cosynthesis for fast design convergence
 In ISPD ’06: Proceedings of the 2006 international symposium on Physical design
, 2006
"... As technology advances, the metal width decreases while the global wire length increases. This trend makes the resistance of the power wire increase substantially. Further, the threshold voltage scales nonlinearly, raising the ratio of the threshold voltage to the supply voltage and making the volta ..."
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Cited by 8 (2 self)
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As technology advances, the metal width decreases while the global wire length increases. This trend makes the resistance of the power wire increase substantially. Further, the threshold voltage scales nonlinearly, raising the ratio of the threshold voltage to the supply voltage and making the voltage (IR) drop in the power/ground (P/G) network a serious problem in modern IC design. Traditional P/G network analysis methods are often very computationally expensive, and it is thus not feasible to cosynthesize P/G network with floorplan. To make the cosynthesis feasible, we need not only an efficient, effective, and flexible floorplanning algorithm, but also a very efficient, yet sufficiently accurate P/G network analysis method. In this paper, we present a method for floorplan and P/G network cosynthesis based on an efficient P/G network analysis scheme and the B*tree floorplan representation. We integrate the cosynthesis into a commercial design flow to develop an effective power integrity (IRdrop) driven design methodology. Experimental results based on a realworld circuit design and the MCNC benchmarks show that our design methodology successfully fixes the IRdrop errors earlier at the floorplanning stage and thus enables the singlepass design convergence.
Analog placement based on novel symmetryisland formulation
 In Proc. 44th ACM/IEEE Design Automation Conf
, 2007
"... In this paper, we present the first amortized lineartime packing algorithm for the placement with symmetry constraints. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B*tree ..."
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Cited by 6 (3 self)
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In this paper, we present the first amortized lineartime packing algorithm for the placement with symmetry constraints. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B*tree representation, we propose automatically symmetricfeasible B*trees (ASFB*trees) to directly model the placement of a symmetry island. Unlike the previous works that can handle only 1D symmetry constraints, our ASFB*tree is the first in the literature to additionally consider 2D symmetry. We then present hierarchical B*trees (HB*trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetry modules. Unlike the previous works, our approach can guarantee the close proximity of symmetry modules and significantly reduce the search space based on the symmetryisland formulation. In particular, the packing time for an ASFB*tree or an HB*tree is the same as that for a plain B*tree (only amortized linear) and much faster than previous works which need at least loglinear time. Experimental results show that our approach achieves the best published quality and runtime efficiency for analog placement.
Multibend bus driven floorplanning
 INTEGRATION, THE VLSI JOURNAL 41 (2008) 306–316
, 2008
"... In this paper, the problem of busdriven floorplanning is addressed. Given a set of blocks and bus specifications (the width of each bus and the blocks that the bus need to go through), we will generate a floorplan solution such that all the buses go through their blocks, with the area of the floorp ..."
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Cited by 4 (0 self)
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In this paper, the problem of busdriven floorplanning is addressed. Given a set of blocks and bus specifications (the width of each bus and the blocks that the bus need to go through), we will generate a floorplan solution such that all the buses go through their blocks, with the area of the floorplan and the total area of the buses minimized. The approach proposed is based on a simulated annealing framework. Using the sequence pair representation, we derived and proved some necessary conditions for feasible buses, for which we allow 0bend, onebend, or twobend. A checking will be performed to identify those buses that cannot be placed simultaneously. Finally, a solution will be generated giving the coordinates of the modules and the buses. Comparing with the results of the most updated work on this problem by Xiang et al. [Busdriven floorplanning, in: Proceedings of IEEE International Conference on ComputerAided Design, 2003, pp. 66–73], our algorithm can handle buses going through many blocks and the dead space of the floorplan obtained is also reduced. For example, if the buses have to go through more than 10 blocks, the approach in Xiang et al. [Busdriven floorplanning, in: Proceedings of IEEE International Conference on ComputerAided Design, 2003, pp. 66–73] is not able to generate any solution while our algorithm can still give solutions of good quality.
Selected SequencePair: An efficient decodable packing representation in linear time using SequencePair
 Proc. ASPDAC 2003
, 2003
"... Abstract — In this paper, we propose “selected sequencepair” (SSP), a sequencepair (seqpair) with the limited number of subsequences called adjacent crosses. Its features are: (1) The smallest packing based on a given SSP can be obtained in O(n) time, where n is the number of rectangles. (2) An a ..."
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Abstract — In this paper, we propose “selected sequencepair” (SSP), a sequencepair (seqpair) with the limited number of subsequences called adjacent crosses. Its features are: (1) The smallest packing based on a given SSP can be obtained in O(n) time, where n is the number of rectangles. (2) An arbitrary packing can be represented by SSP. (3) The total representation number of SSP of size n is not more than that of rectangular dissection of the same size with n − ⌊ √ 4n−1 ⌋ empty rooms (the necessary number of empty rooms to represent an arbitrary packing). To realize these features of SSP, we propose an algorithm to enumerate all adjacent crosses on a seqpair in linear time of n+k (k is the number of adjacent crosses). Also we apply a conventional method to convert a seqpair without adjacent crosses to an equivalent Qsequence, representation of rectangular dissection, in O(n + k) time. A move operation to obtain an adjacent solution efficiently is proposed to perturb SSP for Simulated Annealing. From experimental results, we confirmed the proposed method was carried out in linear time and was more efficient than the conventional method when SSP size got bigger. I.
Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence
"... Abstract—As technology advances, the metal width decreases while the global wire length increases. This trend makes the resistance of the power wire increase substantially. Furthermore, the threshold voltage scales nonlinearly, raising the ratio of the threshold voltage to the supply voltage and mak ..."
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Cited by 2 (1 self)
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Abstract—As technology advances, the metal width decreases while the global wire length increases. This trend makes the resistance of the power wire increase substantially. Furthermore, the threshold voltage scales nonlinearly, raising the ratio of the threshold voltage to the supply voltage and making the voltage (IR) drop in the power/ground (P/G) network a serious problem in modern IC design. Traditional P/G networkanalysis methods are often very computationally expensive, and it is, thus, not feasible to cosynthesize P/G network with floorplan. To make the cosynthesis feasible, we need not only an efficient, effective, and flexible floorplanning algorithm but also a very efficient yet sufficiently accurate P/G networkanalysis method. In this paper, we present a method for floorplan and P/G network cosynthesis based on an efficient P/G networkanalysis scheme and the B∗tree floorplan representation. We integrate the cosynthesis into a commercial design flow to develop an effective powerintegrity (IR drop)driven design methodology. Experimental results based on a realworld circuit design and the MCNC benchmarks show that our design methodology successfully fixes the IRdrop errors earlier at the floorplanning stage and, thus, enables the singlepass design convergence. Index Terms—Electromigration, floorplanning, IR drop, physical design, power/ground (P/G) analysis, power integrity, simulated
Modern floorplanning with boundary clustering constraint*
"... With the development of SOC designs, modern floorplanning typically needs to provide extra options to meet the different emerging requirements in the hierarchical designs, such as boundary constraint for I/O connection, clustering constraint for performance and reliability, etc. This paper addresses ..."
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With the development of SOC designs, modern floorplanning typically needs to provide extra options to meet the different emerging requirements in the hierarchical designs, such as boundary constraint for I/O connection, clustering constraint for performance and reliability, etc. This paper addresses modern floorplanning with boundary clustering constraint. It has been empirically shown that the modern constraints extremely restrict the solution space; that is, a large number of randomly generated floorplans might be infeasible. In order to effectively search the feasible solutions, the feasible conditions based on B*tree representation with boundary clustering constraint are investigated. The properties, coupled with an efficient simulated annealing algorithm, provide the way to produce feasible floorplans by dynamic repairing, which can transform an infeasible solution into a feasible one if the constraint is violated. Our algorithm is verified by using the MCNC and GSRC benchmarks, and the empirical results show that our algorithm can obtain promising solutions in acceptable time. 1.
Analog Placement Based on SymmetryIsland Formulation
"... Abstract—To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity ..."
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Abstract—To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetricfeasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first lineartimepacking algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B ∗tree representation, we propose automatically symmetricfeasible (ASF) B ∗trees to directly model the placement of a symmetry island. We then present hierarchical B ∗trees (HB ∗trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetryisland formulation. In particular, the packing time for an ASFB ∗tree or an HB ∗tree is the same as that for a plain B ∗tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the bestpublished quality and runtime efficiency for analog placement. Index Terms—Analog circuit, floorplanning, physical design, placement. I.
Packing Floorplan Representations
"... As technology advances, design complexity is increasing and the circuit size is getting larger. To cope with the increasing design complexity, hierarchical design and IP modules are widely used. This trend makes module floorplanning/placement much more critical to the quality of a VLSI design than e ..."
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As technology advances, design complexity is increasing and the circuit size is getting larger. To cope with the increasing design complexity, hierarchical design and IP modules are widely used. This trend makes module floorplanning/placement much more critical to the quality of a VLSI design than ever. A fundamental problem to floorplanning/placement lies in the representation of geometric relationship among