Results 1  10
of
84
Power minimization in IC design: principles and applications,"
 ACM Transactions on Design Automation of Electronic Systems,
, 1996
"... Abstract Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for des ..."
Abstract

Cited by 200 (31 self)
 Add to MetaCart
(Show Context)
Abstract Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing design ers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.
HighLevel Power Modeling, Estimation, and Optimization
 IEEE Trans. On Computer Aided Design
, 1998
"... Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the othe ..."
Abstract

Cited by 106 (12 self)
 Add to MetaCart
(Show Context)
Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand highspeed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of highend products to keep power under control, due to the increased costs of packaging and cooling this type of devices. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of lowpower VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature. Index Terms — Behavioral and logic synthesis, low power design, power management. I.
A survey of optimization techniques targeting low power circuits
 in Proc. Design Automation Conf
, 1995
"... Abstract—We survey stateoftheart optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered. Keywords—low power, optimization, synthesis I. ..."
Abstract

Cited by 77 (0 self)
 Add to MetaCart
(Show Context)
Abstract—We survey stateoftheart optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered. Keywords—low power, optimization, synthesis I.
G.De Micheli, ”State assignment for low power dissipation
 Custom Integrated Circuits Conference
, 1994
"... ..."
(Show Context)
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits
 ACM/IEEE 31st Design Automation Conference
, 1994
"... We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a nonlinear system of equations of size N , where the variables correspond to state line probabilities. We show that the approximation method is within 3% o ..."
Abstract

Cited by 39 (1 self)
 Add to MetaCart
We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a nonlinear system of equations of size N , where the variables correspond to state line probabilities. We show that the approximation method is within 3% of the exact ChapmanKolmogorov method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies. 1 Introduction The average power dissipation of a circuit, like its area or speed, may be significantly improved by changing the architecture or the technology of the circuit. But once these architectural or technological improvements have been made, it is the switching of the logic that will ultimately determine its power dissipation. Methods for the power estimation of logiclevel combinational circuits based on switching activity estimation (e.g. [2], [4]) have been presented previously. Power ...
A mathematical basis for powerreduction in digital VLSI systems,”
 IEEE Trans. Circuits Syst. II,
, 1997
"... ..."
(Show Context)
The impact of pipelining on energy per operation in fieldprogrammable gate arrays
 In Proceedings of the International Conference on FieldProgrammable Logic and Applications
, 2004
"... Abstract. This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18µm CMOS lowcost FPGA (Xilinx XC2S200). The results are obtained by both m ..."
Abstract

Cited by 28 (6 self)
 Add to MetaCart
(Show Context)
Abstract. This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18µm CMOS lowcost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendorsupplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40 % and 90%. Further reduction in energy consumption can be achieved by poweraware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages. 1
An improved algorithm for minimumarea retiming
 In Proc. Design Automation Conf
, 1997
"... The concept of improving the timing behavior of a circuit by relocating flipflops is called retiming and was first presented by Leiserson and Saxe. The ASTRA algorithm proposed an alternative view of retiming using the equivalence between retiming and clock skew optimization. This work defines the ..."
Abstract

Cited by 22 (6 self)
 Add to MetaCart
(Show Context)
The concept of improving the timing behavior of a circuit by relocating flipflops is called retiming and was first presented by Leiserson and Saxe. The ASTRA algorithm proposed an alternative view of retiming using the equivalence between retiming and clock skew optimization. This work defines the relationship between the LeisersonSaxe and the ASTRA approaches and utilizes it to solve the problem of retiming for minimum area. The new algorithm, Minaret, uses the linear programming formulation of the LeisersonSaxe approach. The underlying philosophy of the ASTRA approach is incorporated to reduce the number of variables and constraints in the linear program. This reduction in the size of the linear program makes Minaret space and time efficient, enabling minimum area retiming of circuits with over 56,000 gates in under 15 minutes. 1
Low Power Architectural Design Methodologies
 PH.D THESIS, MEMORANDUM NO. UCB/ERL M94/62, 30TH
, 1994
"... In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, batteryoperated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another de ..."
Abstract

Cited by 19 (0 self)
 Add to MetaCart
In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, batteryoperated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom  and complexity  to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support lowpower system design. Lowpower techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and systemlevel optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the registertransfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switchlevel accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis.
Finite State Machine Decomposition for Low Power
 In Proceedings of the 35 th Design Automation Conference
, 1998
"... Clockgating techniques have been shown to be very effective in the reduction of the switching activity in sequential logic circuits. In this paper we describe a new clockgating technique based on finite state machine (FSM) decomposition. We compute two subFSMs that together have the same function ..."
Abstract

Cited by 18 (4 self)
 Add to MetaCart
(Show Context)
Clockgating techniques have been shown to be very effective in the reduction of the switching activity in sequential logic circuits. In this paper we describe a new clockgating technique based on finite state machine (FSM) decomposition. We compute two subFSMs that together have the same functionality as the original FSM. For all the transitions within one subFSM, the clock for the other subFSM is disabled. To minimize the average switching activity, we search for a small cluster of states with high stationary state probability and use it to create the small subFSM. This way we will have a small amount of logic that is active most of the time, during which is disabling a much larger circuit, the other subFSM. We provide a set of experimental results that show that power consumption can be substantially reduced, in some cases up to 80%. I.