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28
Lazy Satisfiability Modulo Theories
 JOURNAL ON SATISFIABILITY, BOOLEAN MODELING AND COMPUTATION 3 (2007) 141Â224
, 2007
"... Satisfiability Modulo Theories (SMT) is the problem of deciding the satisfiability of a firstorder formula with respect to some decidable firstorder theory T (SMT (T)). These problems are typically not handled adequately by standard automated theorem provers. SMT is being recognized as increasingl ..."
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Cited by 181 (47 self)
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Satisfiability Modulo Theories (SMT) is the problem of deciding the satisfiability of a firstorder formula with respect to some decidable firstorder theory T (SMT (T)). These problems are typically not handled adequately by standard automated theorem provers. SMT is being recognized as increasingly important due to its applications in many domains in different communities, in particular in formal verification. An amount of papers with novel and very efficient techniques for SMT has been published in the last years, and some very efficient SMT tools are now available. Typical SMT (T) problems require testing the satisfiability of formulas which are Boolean combinations of atomic propositions and atomic expressions in T, so that heavy Boolean reasoning must be efficiently combined with expressive theoryspecific reasoning. The dominating approach to SMT (T), called lazy approach, is based on the integration of a SAT solver and of a decision procedure able to handle sets of atomic constraints in T (Tsolver), handling respectively the Boolean and the theoryspecific components of reasoning. Unfortunately, neither the problem of building an efficient SMT solver, nor even that
A decision procedure for bitvector arithmetic
 IN PROCEEDINGS OF THE 35TH DESIGN AUTOMATION CONFERENCE
, 1998
"... Bitvector theories with concatenation and extraction have been shown to be useful and important for hardware verification. We have implemented an extended theory which includes arithmetic. Although deciding equality in such a theory is NPhard, our implementation is efficient for many practical e ..."
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Cited by 61 (3 self)
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Bitvector theories with concatenation and extraction have been shown to be useful and important for hardware verification. We have implemented an extended theory which includes arithmetic. Although deciding equality in such a theory is NPhard, our implementation is efficient for many practical examples. We believe this to be the first such implementation which is efficient, automatic, and complete.
Deciding bitvector arithmetic with abstraction
 IN PROC. TACAS 2007
, 2007
"... We present a new decision procedure for finiteprecision bitvector arithmetic with arbitrary bitvector operations. Our procedure alternates between generating under and overapproximations of the original bitvector formula. An underapproximation is obtained by a translation to propositional log ..."
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Cited by 58 (24 self)
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We present a new decision procedure for finiteprecision bitvector arithmetic with arbitrary bitvector operations. Our procedure alternates between generating under and overapproximations of the original bitvector formula. An underapproximation is obtained by a translation to propositional logic in which some bitvector variables are encoded with fewer Boolean variables than their width. If the underapproximation is unsatisfiable, we use the unsatisfiable core to derive an overapproximation based on the subset of predicates that participated in the proof of unsatisfiability. If this overapproximation is satisfiable, the satisfying assignment guides the refinement of the previous underapproximation by increasing, for some bitvector variables, the number of Boolean variables that encode them. We present experimental results that suggest that this abstractionbased approach can be considerably more efficient than directly invoking the SAT solver on the original formula as well as other competing decision procedures.
RTLDatapath Verification using Integer Linear Programming
 In Proceedings of the IEEE VLSI Design Conference
, 2002
"... Satisfiability of complex wordlevel formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware description language (HDL), like Verilog or VHDL, usually this problem is solved in ..."
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Cited by 51 (5 self)
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Satisfiability of complex wordlevel formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware description language (HDL), like Verilog or VHDL, usually this problem is solved in the Boolean domain, using Boolean solvers. These engines often show a poor performance for data path verification. Instead of solving the problem at the bitlevel, a method is proposed to transform conjunctions of bitvector equalities and inequalities into sets of integer linear arithmetic constraints. It is shown that it is possible to correctly model the modulo semantics of HDL operators as linear constraints. Integer linear constraint solvers are used as a decision procedure for bitvector arithmetic. In the implementation we focus on verification of arithmetic properties of VerilogHDL designs. Experimental results show considerable performance advantages over highend Boolean SAT solver approaches. The speedup on the benchmarks studied is several orders of magnitude.
A Survey of Automated Techniques for Formal Software Verification
 TRANSACTIONS ON CAD
, 2008
"... The software in an electronic system is often the greatest concern with respect to quality and design flaws. Formal verification tools can provide a guarantee that a design is free of specific flaws. We survey algorithms that perform automatic, static analysis of software to detect programming erro ..."
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Cited by 51 (5 self)
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The software in an electronic system is often the greatest concern with respect to quality and design flaws. Formal verification tools can provide a guarantee that a design is free of specific flaws. We survey algorithms that perform automatic, static analysis of software to detect programming errors or prove their absence. The three techniques we consider are static analysis with abstract domains, model checking, and bounded model checking. We provide a short tutorial on the these techniques, highlighting their differences when applied to practical problems. We also survey the tools that are available implementing these techniques, and describe their merits and shortcomings.
Binary decision diagrams in theory and practice
, 2001
"... Decision diagrams (DDs) are the stateoftheart data structure in VLSI CAD and have been successfully applied in many other fields.DDs are widely used and are also integrated in commercial tools.This special section comprises six contributed articles on various aspects of the theory and application ..."
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Cited by 31 (7 self)
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Decision diagrams (DDs) are the stateoftheart data structure in VLSI CAD and have been successfully applied in many other fields.DDs are widely used and are also integrated in commercial tools.This special section comprises six contributed articles on various aspects of the theory and application of DDs.As preparation for these contributions, the present article reviews the basic definitions of binary decision diagrams (BDDs). We provide a brief overview and study theoretical and practical aspects.Basic properties of BDDs are discussed and manipulation algorithms are described.Extensions of BDDs are investigated and by this we give a deeper insight into the basic data structure.Finally we outline several applications of BDDs and their extensions and suggest a number of articles and books for those who wish to pursue the topic in more depth.
A lazy and layered SMT(BV) solver for hard industrial verification problems
 In Computer Aided Verification (CAV), LNCS
, 2007
"... Abstract. Rarely verification problems originate from bitlevel descriptions. Yet, most of the verification technologies are based on bit blasting, i.e., reduction to boolean reasoning. In this paper we advocate reasoning at higher level of abstraction, within the theory of bit vectors (BV), where s ..."
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Cited by 21 (5 self)
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Abstract. Rarely verification problems originate from bitlevel descriptions. Yet, most of the verification technologies are based on bit blasting, i.e., reduction to boolean reasoning. In this paper we advocate reasoning at higher level of abstraction, within the theory of bit vectors (BV), where structural information (e.g. equalities, arithmetic functions) is not blasted into bits. Our approach relies on the lazy Satisfiability Modulo Theories (SMT) paradigm. We developed a satisfiability procedure for reasoning about bit vectors that carefully leverages on the power of boolean SAT solver to deal with components that are more naturally “boolean”, and activates bitvector reasoning whenever possible. The procedure has two distinguishing features. First, it relies on the online integration of a SAT solver with an incremental and backtrackable solver for BV that enables dynamical optimization of the reasoning about bit vectors; for instance, this is an improvement over static encoding methods which may generate smaller slices of bitvector variables. Second, the solver for BV is layered (i.e., it privileges cheaper forms of reasoning), and it is based on a flexible use of term rewriting techniques. We evaluate our approach on a set of realistic industrial benchmarks, and demonstrate substantial improvements with respect to stateoftheart boolean satisfiability solvers, as well as other decision procedures for SMT(BV). 1
P.: Structural Testing of Executables
 In: ICST 2008. IEEE Computer Society, Los Alamitos
, 2008
"... Verification is usually performed on a highlevel view of the software, either specification or program source code. However in certain circumstances verification is more relevant when performed at the machine code level.This paper focuses on automatic test data generation from a standalone executab ..."
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Cited by 20 (8 self)
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Verification is usually performed on a highlevel view of the software, either specification or program source code. However in certain circumstances verification is more relevant when performed at the machine code level.This paper focuses on automatic test data generation from a standalone executable. Lowlevel analysis is much more difficult than highlevel analysis since even the controlflow graph is not available and bitlevel instructions have to be modelled faithfully. We show how “pathbased ” structural test data generation can be adapted from structured language to machine code, using both stateoftheart technologies and innovative techniques. Our results have been implemented in a tool named OSMOSE and encouraging experiments have been conducted. 1.
Formal Verification of WordLevel Specifications
 Proc. Design Automation and Test in Europe (DATE
, 1999
"... Formal verification has become one of the most important steps in circuit design. In this context the verification of highlevel Hardware Description Languages (HDLs), like VHDL, gets increasingly important. In this paper we present a complete set of datapath operations that can be formally verified ..."
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Cited by 13 (1 self)
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Formal verification has become one of the most important steps in circuit design. In this context the verification of highlevel Hardware Description Languages (HDLs), like VHDL, gets increasingly important. In this paper we present a complete set of datapath operations that can be formally verified based on WordLevel Decision Diagrams (WLDDs). Our techniques allow a direct translation of HDL constructs to WLDDs. We present new algorithms for WLDDs for modulo operation and division. These operations turn out to be the core of our efficient verification procedure. Furthermore, we prove upper bounds on the representation size of WLDDs guaranteeing effectiveness of the algorithms. Our verification tool is totally automatic and experimental results are given to demonstrate the efficiency of our approach. 1