• Documents
  • Authors
  • Tables
  • Log in
  • Sign up
  • MetaCart
  • DMCA
  • Donate

CiteSeerX logo

Advanced Search Include Citations
Advanced Search Include Citations | Disambiguate

Incremental Formal Design Verification (0)

by G M Swamy, R K Brayton
Add To MetaCart

Tools

Sorted by:
Results 1 - 4 of 4

Incremental Methods for FSM Traversal

by Gitanjali M. Swamy, Robert K. Brayton, Vigyan Singhal - in Proc. Intl. Conf. on Computer Design , 1995
"... Computing the set of reachablestates of a finite state machine, is an important component of many problems in the synthesis, and formal verification of digital systems. The process of design is usually iterative, and the designer may modify and recompute information many times, and reachability is c ..."
Abstract - Cited by 7 (2 self) - Add to MetaCart
Computing the set of reachablestates of a finite state machine, is an important component of many problems in the synthesis, and formal verification of digital systems. The process of design is usually iterative, and the designer may modify and recompute information many times, and reachability is called each time the designer modifies the system, because current methods for reachability analysis are not incremental. Unfortunately, the representation of the reachable states that is currently used [1] in synthesis and verification, is inherently non-updatable. We solve this problem by presenting alternate ways to represent the reachable set, and incremental algorithms that can update the new representation each time the designer changes the system. The incremental algorithms use the reachable set computed at a previous iteration, and information about the changes to the system to update it, rather than compute the reachable set from the beginning. This results in computational savings, ...
(Show Context)

Citation Context

...e correct final answer to an LFP, when supplied to any algorithm to compute it. Figure 3 illustrates this point. A similar statement can be made about GFP computations, as shown by Swamy, and Brayton =-=[9]-=-. Definition 4 Cproject Operator[10]: The cproject project operator can be used to extract a tree subset graph of an acyclic graph. The cproject operator is a selection operator, which when given a re...

Incremental Methods for Formal Verification and Logic Synthesis

by Gitanjali Meher Swamy , 1996
"... IC design is an iterative process; the initial specification of a design is rarely complete and correct. The designer begins with a preliminary and usually incorrect sketch (possibly from a previous generation design), and iteratively refines and corrects it. Usually, refinements are small, and the ..."
Abstract - Cited by 6 (0 self) - Add to MetaCart
IC design is an iterative process; the initial specification of a design is rarely complete and correct. The designer begins with a preliminary and usually incorrect sketch (possibly from a previous generation design), and iteratively refines and corrects it. Usually, refinements are small, and there is much common information between successive design iterations. The current genre of CAD tools do not take into account this iterative nature of design. For each change made to the design, the design is re-verified and re-optimized without taking advantage of information from previous iterations. This leads to inefficient performance. In this thesis, we propose the paradigm of incremental algorithms for CAD. Incremental algorithms use information from a...
(Show Context)

Citation Context

...cision. Also, we deal with more general multi-valued functions [48], rather than just binary. The techniques presented here can be used to drive the incremental verification algorithms of Swamy et al =-=[49]-=- [50] and Sokolosky et al [32]. These use information about the similarities between two designs to speed up the verification process. This chapter is organized as follows. Section 3.2 contains exact ...

Identifying Common Substructure for Incremental Methods

by Stephen A. Edwards, Gitanjali M. Swamy, Robert K. Brayton , 1996
"... In this paper we solve the problem of identifying a "matching" between two logic circuits or "networks". A matching is a functions that maps each gate or "node" in the new circuit into one in the old circuit (if a matching does not exist it maps it to null). We present ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
In this paper we solve the problem of identifying a "matching" between two logic circuits or "networks". A matching is a functions that maps each gate or "node" in the new circuit into one in the old circuit (if a matching does not exist it maps it to null). We present both an exact and a heuristic way to solve the maximal matching problem. The matching problem does not require any input correspondences; the purpose is to identify structurally identical regions in the networks. We apply this solution to the problem of incremental design. Logic design is usually an iterative process where errors are corrected and optimizations performed repeatedly. A designer rectifies, re-optimizes, and rechecks a design many times. In practice, it is common for small, incremental changes to be made to the design, rather than changing the entirety of the design. Currently, each time the system is modified, the entire set of computations (synthesis, verification) are repeated from the beginning. This re...
(Show Context)

Citation Context

...cision. Also, we deal with more general multi-valued functions [6], rather than just binary. The techniques presented here can be used to drive the incremental verification algorithms of Swamy et a.l =-=[7]-=- [8] and Sokolosky et al. [9]. These use information about the similarities between two designs to speed up the verification process. 3 Table Matching The nodes in our networkshave discrete-valued fun...

Incremental CTL Model Checker for Fair States

by Victor R. L. Shen
"... ..."
Abstract - Add to MetaCart
Abstract not found
Powered by: Apache Solr
  • About CiteSeerX
  • Submit and Index Documents
  • Privacy Policy
  • Help
  • Data
  • Source
  • Contact Us

Developed at and hosted by The College of Information Sciences and Technology

© 2007-2019 The Pennsylvania State University